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Home > About Cadence > Newsroom > Cadence Articles > High-Powered Experts Discuss Low-Power Design
Industry experts gather to discuss the challenges of power-efficient design—from silicon to system

    

Low-Power Summit Proceedings
 

This exciting summit featured multiple technology tracks and a total of 17 presentations from many PFI member companies, including Global Unichip, Si2, ARM, Calypto, Freescale, Cadence, Mindtree, Sonics, Virage, Faraday, Alchip, and Magma.

All the proceedings are available in both PDF and video format on the Power Forward Initiative web site. View the proceedings »

(Viewing requires a PFI site membership. You can create an account here.)

Additional resources
Cadence hosted the second annual Power Forward Initiative (PFI) Low-Power summit in Silicon Valley. Engineers, ecosystem partners and PFI member companies gathered to share examples, findings and best practices around the critical new topic of low-power design. The year’s event built on the success of previous summits held last October 2008 in the Silicon Valley and in June 2009 in the United Kingdom.

John Bruggeman, Cadence’s new CMO, kicked off the summit. He emphasized the daunting challenges presented by low-power and power-aware design, and the importance of supporting and contributing to the work of organizations such as PFI. “PFI is leading the drive to find solutions for one of the daunting engineering challenges facing the industry,” noted Bruggeman. “Power-aware design extends from silicon to system, and it is bigger than any one company—it requires everyone working as a community.”

The audience had an opportunity to get an up-close view of leading-edge power-aware design from industry leaders. Among the many presenters, Albert Li of GUC showed his company’s low-power technology utilizing a technology demonstration board performing audio and video decoding in multiple operating modes. The Si2 presentation focused on the efforts enable interoperability and what engineers and ecosystem partners need to be aware of when working in a multi-format environment. Qi Wang, a Cadence Architect and a co-chair of the Si2 working body, listed a number of documents available on the Si2 site that detail their studies and findings on interoperability.

The summit also included a panel discussion on the evolution of low-power design, and the opportunities and challenges that is presents to the industry. Panel members came from all across the spectrum of the design chain, including representatives from AMD, Cadence, Sonics, and WiPro. One constant theme was that power-aware design is no longer an optional consideration; it is a must-have part of design.

Other tracks included implementation and signoff, and design and verification. Multiple technical presentations were held in each track from PFI member companies, including Global Unichip, Si2, ARM, Calypto, Freescale, Cadence, Mindtree, Sonics, Virage, Faraday, Alchip, and Magma.

Cadence plans to support future PFI activities. Watch for details on coming events, as well as information on how your company can become a PFI member and participate in guiding the continuing evolution of power-aware and low-power design.

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