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Cut through Complexity

New Incisive Enterprise Verifier lets design and verification engineers jumpstart verification to improve quality and slash time to complex chip sign-off


Simulation has become the most common technology for verifying complex chips. Formal analysis, on the other hand, is seeing more adoption but has not yet fully found its way into mainstream verification. This is despite the fact that formal analysis enables deeper bug hunting, including the ability to root out tough-to-find corner-case bugs. Now, Cadence® Incisive® Enterprise Verifier combines the fine-grained bug-hunting capabilities of formal analysis with the capacity and ease-of-use of simulation. As a result, design and verification engineers can begin meaningful verification much earlier in the development process, reducing overall project time and increasing quality.

The new dual-power capabilities of formal plus simulation represents a major leap forward in verification. In addition to delivering the standalone capabilities of simulation and formal analysis, Incisive Enterprise Verifier goes beyond the sum of these two parts to deliver capabilities not found in either technology. For example, it can "ping-pong" back and forth between the formal-analysis and simulation engines. The tight integration of simulation and formal analysis also brings three foundational dual-power capabilities that support multiple use models:

Property-driven simulation — can actually drive pure random stimulus directly into the design using only properties. Whereas properties typically are passive and act as monitors in simulations, now the properties are active. This capability is especially helpful in the design bring-up stage, where property-driven simulation allows engineers to start finding bugs from day one.

Formal-assisted simulation — enables engineers to identify an interesting state they want to reach within the design. The formal analysis engines are smart enough to identify the shortest path to this state, thereby eliminating the need for the user to manually develop a simulation testbench to reach that point. Due to the probabilistic nature of simulation-based stimulus it would be harder to reach the state with simulation alone. Using formal-assisted simulation automates the process, ensuring that users are more productive.

Simulation-assisted formal — lets engineers stop the simulation after reaching a certain point in time, and then turn on the formal analysis capability to take a deeper look and explore around that state. This capability makes it possible to find deep bugs and coverage points without facing the capacity limits of traditional formal analysis tools. After the formal analysis, Incisive Enterprise Verifier can go back into simulation mode, alternating between simulation and formal in a single run.

The most dramatic development is the ability Incisive Enterprise Verifier provides to start verification at the outset of a project—even before testbench development. "We use both formal analysis and testbench simulation based on a multi-language approach in our standard verification flow," said Mirella Negro Marcigaglia, MMS Microcontroller Division verification manager, at STMicroelectronics. "Incisive Enterprise Verifier combines these technologies to accelerate tasks that we used to perform much later in the development process, thereby reducing our project verification time."

In short, all these benefits of combining formal analysis with simulation engines enable designers and verification engineers to:
  • Bring designs up faster
  • Boost predictability by generating more metrics to assist with verification closure
  • Improve quality by finding more bugs—and deeper bugs—in the design



 

"With this combination you are able to find bugs and gather verification metrics earlier in the process," said Sarah Lynne Cooper Lundell, senior product marketing manager at Cadence. "You don't have to wait for a testbench to be available to do deeper verification. Plus, when the testbench environment becomes available, you can better focus your efforts because you are working with cleaner blocks. Incisive Enterprise Verifier provides sign-off metrics that increase your overall confidence level that you are done."

With easy set-up, automatic operation for most users, fine-grain control for expert users, and new assertion debug capabilities, Incisive Enterprise Verifier provides a unique new, tightly integrated solution to the market to improve overall productivity and provide quality gains to design and verification engineers. The net effect of this new dual-power solution is improved productivity and predictable sign-off. And the new capabilities delivered by Incisive Enterprise Verifier also represents the future of verification, where meaningful verification starts early in process by design and verification engineers.

For more information or to request a product overview presentation contact Cadence.

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