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Cadence and Hitachi Achieve Unparalleled Compression Efficiency to Speed Silicon Realization

The fundamental challenge in silicon realization is getting from concept to silicon quickly and cost-effectively—without sacrificing quality. To keep mutual customers ahead of the silicon and SoC manufacturing curve with higher product quality and lower development costs, Hitachi and Cadence have collaborated to deliver a top-notch test methodology that achieves 1,100x the compression efficiency of other methods. This has exceeded goals nearly 4 years ahead of industry expectations. Mutual customers now have a concurrent design-for-manufacturing optimization flow that yields first-pass silicon success.

Cadence provided Hitachi with Encounter Test, which combines SDF-based dynamic test pattern generation, OPMISR compression technology, advanced pattern fault modeling, and volume and precision diagnostics to achieve extremely accurate fault modeling that eliminates test escapes. Combining these capabilities with Hitachi's HBIST compression technology enabled greater than 99% fault coverage while achieving an unparalleled 1,100x compression rate.

"Hitachi has collaborated with Cadence to deliver an innovative next-generation solution for developing advanced nanometer designs while also achieving significant reduction in test cost and higher test quality," said Dr. Nobuo Tamba, General Manager of the Design & Development Operation, Micro Device Division, Hitachi, Ltd. "The collaboration has delivered an unparalleled 1,100x compression rate, which not only meets our own challenging manufacturing demands, but also the quality demands of customers in markets where reliability is mission-critical."


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The achievement allows Hitachi to manufacture and deliver LSIs to industries such as computers, communications, transportation, medical devices, and other infrastructure equipment, all of which demand the most rigorous testing and quality assurance. The joint technology also enables faster yield ramp and more accurate and efficient vector sets than previous solutions, eliminating the need for time-consuming iterative debug and refinement loops to achieve high-quality test patterns.

Native to the Encounter RTL Compiler global synthesis environment, Encounter Test provides a unified platform that expands the definition of silicon quality to include area, timing, power, and testability. Encounter Test comprises three product technologies: Encounter DFT Architect, Encounter True-Time ATPG, and Encounter Diagnostics. Because these advanced capabilities augment existing solutions, Cadence test technology increases ROI for companies like Hitachi.

"Cadence Encounter Test solutions operate at performance specs that are well ahead of industry requirements," said Sanjiv Taneja, Vice President of Encounter Test at Cadence. "This reflects our continuing commitment to solving customer design and manufacturing test challenges, no matter how big or complex, with silicon realization solutions that exceed expectations, streamline the entire DFM process, and improve cost-effectiveness."

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