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Open Verification Methodology delivers on the SystemVerilog interoperability promise

With devices becoming ever more complex, engineers are under increasing pressure to speed deployment of verification methods. SystemVerilog promised to fill this need, but verification teams quickly discovered that a standard language alone was not enough. To facilitate true SystemVerilog interoperability, Cadence and Mentor collaborated to deliver a standard class library and methodology.

The result is the first open, interoperable, and proven verification methodology—the Open Verification Methodology. It delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP, transaction-level and RTL models, and full integration with other languages commonly used in production flows. It defines a framework for reusable Verification IP and tests, is 100% IEEE 1800 SystemVerilog compliant, and provides building blocks (objects) and a common set of verification-related utilities.

The Open Verification Methodology combines the best of the Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology and the Mentor Advanced Verification Methodology, and is usable on two-thirds of the world's SystemVerilog systems. It will also facilitate the development and usage of plug-and-play Verification IP written in the SystemVerilog, SystemC®, and e languages.

As a truly open methodology, it solves one of the biggest issues facing SystemVerilog adoption today—it gives customers confidence that their investments in verification will be reusable in the future. Having a methodology that works on a number of widely installed simulators and verification tools assures verification teams they can enjoy the benefits of SystemVerilog now.

All of these advantages explain why the Open Verification Methodology was among All of these advantages explain why the Open Verification Methodology was among Electronic Design's 2007 BEST EDA Winners. 2007 BEST EDA Winners.

"With the Open Verification Methodology, Cadence and Mentor are delivering an efficient SystemVerilog-based, tool-independent solution to help solve our combined customers' key design challenges," said Michal Siwinski, group director, Advanced Verification and Logic Design Team Solution at Cadence. "The industry as a whole will benefit with a much higher degree of interoperability, verification IP development and reuse, and ease of integration."



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