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Home > About Cadence > Newsroom > Cadence Articles > Cadence Announces New Silicon-Validated Digital End-to-End Flow
Cadence Announces New Silicon-Validated Digital End-to-End Flow

Spurring the industry to take the next leap forward in digital design, implementation, and verification, Cadence has just unleashed a new digital end-to-end flow, proven at 28 nanometers, that yields both performance and time-to-market breakthroughs. Today’s announcement builds on the momentum of extensive metric-driven verification capabilities released earlier this month and broadens the scope of the Cadence approach to Silicon Realization.

Designers now have a faster, more deterministic path to achieve giga-gate/gigahertz silicon through comprehensive technology integration, core architecture improvements, and algorithm enhancements within a unified design, implementation, and verification flow. Based on award-winning Cadence® Encounter® technologies—and seamlessly integrated with analog/mixed-signal and silicon/package co-design capabilities—the digital end-to-end flow enables designers to consider the entire chip development process holistically. By optimizing design at 28nm, Cadence delivers a predictable path to advanced SoC development so that customers can realize the cost benefits of smaller geometries.

"The complexity of 28nm design, coupled with the need to support complex giga-gate/gigahertz requirements, demands an integrated end-to-end flow," said David Desharnais, Senior Director of Silicon Realization Product Marketing at Cadence. "Our unique Silicon Realization approach allows our customers to push their SoC designs to new levels in order to deliver the highest performance silicon for multimedia, communications, and computing applications."

Available now, the new flow supports the Cadence approach to Silicon Realization by enabling unified design and verification intent, higher levels of abstraction, and convergence—from planning to tapeout and through to packaging.

Unified intent
Leading-edge customers are designing at 28nm/32nm process nodes, and Cadence is collaborating with foundries to streamline the handling of the latest design rules. The digital end-to-end flow supports complete, silicon-proven 28nm design rule intent (electrical, physical, DFM) with early tradeoff analysis. This plus intelligent via and pin-density optimizations results in a 2x improvement in routing runtime.

The new flow also captures clock topology intent upfront, and uses physical information to optimize clock gating and balance clock trees during synthesis. With support for the Common Power Format and backed by the Cadence commitment to power format interoperability, designers not only have an easy way to define and verify power intent throughout the entire digital flow, but they also benefit from a production-proven methodology for advanced low-power designs.

"The improved correct-by-construction, multi-objective optimization for low-power designs in the Cadence digital end-to-end flow is a much welcomed addition to the already reputable Cadence low-power implementation capabilities," said Bertrand Debray, VP of Engineering at Sequans Communications. "With this improvement, our design teams can achieve the most optimal results for power, performance, and area."

Enhanced abstraction
Cadence has developed new data abstraction technology that enables entire blocks of digital logic to be modeled simply and accurately, and then optimized across logical and physical domains. These breakthrough algorithms provide giga-gate scalability and boost design productivity, with runtime improvements of 20x or more.

The new digital end-to-end flow provides support for hierarchical low-power and OpenAccess-based mixed-signal abstractions. With hierarchical macro modeling capabilities for complex mixed-signal IP with power management features, designers can apply formal low-power checks at the SoC level. This is a significant advantage over traditional simulation-centric mixed-signal design verification in terms of productivity and quality, as formal checks may identify electrical design bugs that functional simulation cannot catch.

Faster convergence
Engineering change orders (ECOs) can be time consuming and costly when made in the later stages. Cadence automates the ECO process, from synthesis all the way to physical implementation. The new flow offers physically aware, fully automated pre-mask ECO capability to dramatically shorten the design cycle.

With shrinking process nodes and larger, more congested designs, signal integrity and timing closure is a major contributor to design flow runtime. The Cadence digital end-to-end flow introduces an advanced analysis engine that concurrently performs signal integrity and timing analysis, thereby improving convergence with less iteration and speeding up signal integrity closure runtime by 2x.

Since nearly all SoCs today are mixed signal, integration of significant analog and digital content requires a unified database. The Cadence solution is based on the industry standard OpenAccess database used for seamless data and constraints exchange between analog and digital domains. This enables designers to capture and communicate design intent and it eliminates data translations, which reduces design cycle time and boosts productivity of design teams. The new flow also supports accurate mixed-signal static timing analysis and timing-driven optimization at the SoC level, eliminating iterations between digital and analog design teams.

John Williams, Sr. CAD Engineering Manager at Zarlink, said, “The Cadence mixed-signal flow with Encounter Digital Implementation (EDI) System and Virtuoso® custom IC platform integrated on OpenAccess enabled us to design much more productively. We no longer ‘push’ and ‘stream-in’ data between the tools. The ability to see inside AMS blocks as we do floorplanning and chip integration in EDI System helps us achieve design convergence, faster. This is huge improvement from our previous flow.”

3D-IC capabilities
3D-IC design with through-silicon vias (TSVs) holds the promise of higher bandwidths, less power consumption, increased density, lower packaging costs, and the benefits of not having to move an entire SoC to an advanced process node. However, the stacked-die process can introduce some methodology challenges. The Cadence digital end-to-end flow includes the first production release of a fully integrated 3D stacked-die design environment that spans digital, custom, and package domains. With 3D-IC capabilities such die-to-die floorplanning, placement, optimization, and routing—along with in-design signoff extraction, timing, power, and thermal analyses across multiple dies—designers can reduce interconnect bottlenecks, perform necessary performance tradeoffs, and realize the benefits of 3D-IC.

A complete, end-to-end solution
With this new flow, Cadence delivers a true end-to-end digital solution in which integrated tools share common intent specification and multiple levels of abstraction, ensuring convergence with even the most advanced requirements. Customers can now make breakthroughs in performance, power, and packaging to develop truly differentiated mobility-based and multimedia SoCs—efficiently, predictably, and profitably.

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