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Home > About Cadence > Newsroom > Cadence Articles > Cadence Unveils its Latest Encounter RTL-to-GDSII Flow
Cadence Unveils its Latest Encounter RTL-to-GDSII Flow

Cadence has announced new technologies and capabilities in its Encounter digital flow, spanning design through implementation and signoff. These latest enhancements enable high-performance, giga-scale, and 20nm designs.

High-performance design
Cadence has worked with leading IP partners to provide the industry’s best PPA (power, performance, area) on embedded, high-performance processor designs.

The new GigaOpt engine, critical for RTL-to-GDSII core optimization, integrates physical-aware synthesis with physical optimization, enabling faster timing closure and better correlated results. It provides better quality of results (QoR) with a 30% full-flow runtime speed-up for design closure. Enhanced physical synthesis capability enables better QoR and a more convergent RTL-to-GDSII methodology with added support for custom-crafting structured data paths, which takes advantage of regularity to reduce wire length and congestion while boosting performance. New Clock Concurrent Optimization (CCOpt) technology unifies clock tree synthesis with physical optimization, resulting in design performance and total power improvements of 10%, and a 30% reduction in clock tree area.

Giga-scale design
The rapid increase in logic instance count in today’s designs makes design prototyping and implementation a challenge due to additional complexities and runtime limitations. Cadence has introduced the unique patent-pending GigaFlex technology that enables orders of magnitude compression of the design netlist while still retaining area, congestion, and timing accuracy.

New GigaFlex technology handles giga-scale design of 100M instances or more. Designers can now achieve full-chip design prototyping goals in just 10% of the original time required, and they can uncover potential issues earlier in the design flow to produce the most optimal floorplan. Concurrent top- and block-level hierarchical implementation reduces iterations and total design cycle time for giga-scale designs. Automated functional ECO solutions leverage formal technologies to accelerate pre- and post-mask ECOs, which are reduced to mere hours or days through smart hierarchical design handling. New multi-mode/multi-corner timing and signal integrity (SI) signoff-driven ECO technology leverages a multi-CPU backplane to provide fully automated, physical-aware timing ECOs at the full-chip level.

New Encounter Test SmartScan technology enables ultra-low pin-count compression architecture support for multi-core SoC designs. New automation simplifies the design-for-test processes needed for effective logic built-in self-test (LBIST). The introduction of new automatic test pattern generation (ATPG) algorithms that are parallel and scalable enable design teams to harness multi-processor compute solutions to significantly reduce runtimes and generate test patterns that do not exceed power consumption targets during manufacturing test.

20nm design
Cadence has been working very closely with all the key foundries and IDMs to offer a unique correct-by-construction, 20nm design, implementation, and signoff methodology with double-patterning technology support. It covers RTL synthesis, floorplanning and placement, routing, signoff timing, power analysis, test, and physical verification, and provides a fast path to 20nm design closure.

FlexColor, the correct-by-construction double-patterning implementation engine, allows metal shapes in the design to be color-assigned in real time, enabling more flexible implementation of a double-patterning–correct design. This ultimately improves die area efficiency—and enables more effective ECOs—of 20nm double-patterning designs. The Cadence 20nm RTL-to-GDSII methodology has been validated across multiple design styles and tapeouts, with strong support from foundry and IP ecosystem partners.

“We used a number of Cadence tools during the development of the A7L, including RTL Compiler, Conformal LEC, EDI System, Encounter Timing System, and Encounter Power System. The unified digital flow proved robust at 32nm, and despite the fact that this was a very complex design, we achieved first time success."
Chris Day, VP of Marketing and Business Development at Ambarella
“Cadence allowed us to embed some of our key needs and features into their IC design and analysis tools, like Encounter Timing System, enabling us to perform advanced timing system analysis, with unique timing capabilities. Ultimately, this allowed us to deliver the most advanced, sophisticated pace-maker product on the market today.”
David Genzer, Director of IC Design Development at BIOTRONIK
“One of the benefits that we found at Biotronik is that Cadence provides seamless interfaces between Encounter tools. Encounter Timing System, QRC Extraction, and Conformal verification all utilize common files … simplifying usability and speeding up the design cycle tremendously. Today, Cadence is the only vendor that can deliver all this to us in one product.”
David Genzer, Director of IC Design Development at BIOTRONIK
“We have worked with Cadence over the last 5 years to tape out more than 100 low-power designs… to solve low-power challenges from a methodology point of view instead of relying on point tools. We feel confident working with Cadence to bring in more silicon success as well as meet our design specs and time-to-market goals.”
Alex Kuo, Senior Design Manager at Global Unichip Corp.
“Cadence provides a powerful and interoperable digital and analog co-design environment for mixed-signal designs, from design capture to verification, physical implementation, full-chip level integration, extraction and signoff... providing mutual customers with a more cost-effective solution for a quick and accurate design cycle and fast time to market.”
Robert Milkovits, Director of Customer Design Support at TowerJazz
“Using the Cadence mixed-signal solution enabled us to accelerate our design time by 10x compared to the design of a previous chip built in 65 nanometers… we were amazed how much time was saved.”
Rolf Becker, Development Manager at STE
“Ultra low power is the primary focus in the development of the MSP430 micro controller family. We continuously strive to reduce the active and leakage power to enhance the overall system energy efficiency.”

“We recently implemented a design with multi-vt technology, multi-vdd and power-gated partitioning. Using the EDI System Low Power Design Methodology and CPF driven design
flow, remarkable power savings and overall area reduction have been achieved.”
Adi Baumann, IC Design Manager at Texas Instruments.
“Imec is currently implementing a 4G baseband processor, targeting both existing and emerging WLAN as 3GPP-LTE modes, in an advanced CMOS process. The key to achieving
a flexible, high performance, small die size and low power implementation, is our innovative architecture combined with an advanced digital implementation flow capable of tackling our design challenges.”

“Using the Cadence CPF enabled flow results in a high performance and low power design.
In addition, the design iterations are reduced significantly through the advanced timing closure in the EDI System physical implementation flow. We achieve all our design objectives with a
faster time to market.”
Dejonghe Antoine, Program Manager Reconfigurable Radio Baseband of imec
“We have used the Cadence Encounter Test MBIST solution to self-test 104 memories on our most recent BOA project tape out - a 4G Baseband 40nm design - and were very satisfied with the results. We have received excellent support from Cadence and the Encounter Test team throughout the duration of this project. Now, we are in the process of getting the MBIST integrated into our full design flow.”
Jagadeesa Das Arul Mahesh, R&D ASIC Design Engineer at imec
“At Marvell, we have an optimized advanced low power methodology that supports complex power domains in our designs. We use Cadence’s CPF-driven automatic solution from synthesis, implementation to verification on many of our low power tapeouts, and have
achieved significant power savings and design schedule acceleration because of that.”
Jianwen Jin, Director of Physical Design at Marvell

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