Cadence Announces Availability of the First Commercial
DDR4 IP Solution
Today, realizing differentiated SoC products means solving the difficult challenge of designing and integrating memory management IP onto the SoC. The quality of the IP can dramatically impact the performance, power, and signal integrity of the entire SoC and system. To ensure successful SoC development, the IP must have the following attributes:
- High performance: the solution should give intelligent, “full custom” performance with no allowances made for it being a “general purpose” solution
- Full feature set: the solution should have all the necessary features for any of the SoCs that choose to use it
- Flexibility: the solution should be able to be integrated into any SoC quickly and with minimum re-engineering of the SoC
- Comprehensiveness: the solution should be designed with input from customers, suppliers, and standards bodies
- Compatibility: the solution must be compliant with published standards and, in the case of PHY layers, designed for compatibility with package and board implementation
Forward-thinking designers and integrators are now evaluating how to incorporate higher performance memory into their systems, including plans for the emerging DDR4 standard. They need a comprehensive solution that offers the flexibility to implement this emerging standard at a pace that makes both technological and financial sense.
To help designers and integrators overcome these challenges, Cadence now offers a comprehensive DDR4 solution that includes hard and soft PHY IP; controller IP, memory models, verification IP, tools and methodologies, signal integrity reference designs for the package and board, and a full complement of design services from the industry’s leader in memory design expertise. The soft PHY and controller deliver flexibility that can be synthesized to support the full range of frequencies and voltages. Designers can support a pure DDR4 SoC, or combine DDR4 with other technologies like DDR3 or LPDDR2. And, the Cadence integration environment enables customers to model and analyze their target memory topology and verify the behavior of the IP at both the SoC and system levels.
Cadence is uniquely qualified to offer this comprehensive DDR4 IP solution. Having worked with hundreds of customers to integrate earlier generations of DDR-based memory controllers, Cadence and the newly acquired Denali team offer the proven, high-quality IP and sophisticated integration environment required to speed integration, reduce cost, and ensure design manufacturability. Cadence is the only company to support its high-quality IP with an integration environment that spans every aspect of design—from silicon to package to board—to dramatically lower the risk associated with realizing complex DDR4-based SoC designs.
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