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Cadence in the News at DAC 2012

Successful development of advanced node designs requires innovations in technology and methodology that only come through close collaboration across the electronics industry. At DAC 2012, Cadence demonstrates its momentum into the next phase of advanced node design with news of collaborative efforts with key ecosystem partners.

Cadence Collaborates on 3D-IC Design Infrastructure with TSMC
Cadence announces its collaboration with TSMC on 3D-IC design infrastructure development, enabling multi-chip co-design among digital, custom, and package environments that incorporate through-silicon vias (TSVs). Read more »

Cadence Encounter and Virtuoso Design Platforms Receive TSMC Certification for 20nm Readiness
Cadence Encounter digital and Virtuoso custom/analog design platforms achieve TSMC Phase I certification for 20nm design, implementation, and verification/signoff. Read more »

TSMC Qualifies Cadence Physical Verification System for 20nm and 28nm Signoff
TSMC announces that it has qualified the Cadence Physical Verification System for 28nm design signoff and has completed Phase I certification for the TSMC 20nm process. Read more »

Cadence and STMicroelectronics Tape Out 20nm Test Chip
Cadence announces its contributions to STMicroelectronics’ 20nm test chip tapeout, incorporating custom analog and digital methodologies to enable mixed-signal SoC design at this advanced process node. Read more »

Samsung and Cadence Deliver on 20nm Chip and Double Patterning
Samsung and Cadence collaborate to deliver a 20nm design methodology that incorporates double-patterning technology (DPT) for mutual customer deployment and internal test chips. Read more »

GLOBALFOUNDRIES Silicon Validates 28nm AMS Production Design
GLOBALFOUNDRIES announces a flow that provides front-to-back support for advanced analog/mixed-signal design using the latest design automation tools, including Virtuoso and Encounter technologies from Cadence. GLOBALFOUNDRIES also describes design flows jointly developed with Cadence and other EDA partners, certifying both analog and digital “double patterning–aware” flows for its 20nm process. Read more »

Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard
Cadence supports the Accellera Systems Initiative announcement of the Unified Coverage Interoperability Standard (UCIS) version 1.0.
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Learn more about Cadence exhibits, sponsored luncheons and breakfasts, technical sessions and demonstrations, and other events at DAC 2012. Learn more »

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