Just weeks after announcing a unified digital flow across design, implementation, and verification, Cadence delivers a unified custom/analog flow with the latest release of its industry-leading Virtuoso®
custom/analog technologies. Among enhancements to publishing and design-checking software and next-generation waveform viewing, the Cadence custom/analog flow is fortified by three key integrated components: a flow for parasitic-aware design
, a new “in-design” manufacturing signoff tool (Virtuoso DFM
), and a new power and signal integrity management tool (Virtuoso Power System
These features translate into a potential productivity boost of up to 30 percent over the use of point tools. Available immediately with the Virtuoso 6.1.5 release, the new flow delivers a truly holistic approach to analog, custom-digital, and RF design, silicon/package co-design, and mixed-signal design, implementation, and verification—for all process nodes down to 20 nanometers. Parasitic-aware design flow
Analog designers often have to over-design to compensate for unknown parasitics, or wait until the end of the layout cycle to see how layout-dependant effects will impact the design’s performance. The Cadence parasitic-aware design flow allows engineers to determine the affect of their design choices early on, thus eliminating unnecessary design iterations. Analog design teams can use previous knowledge of topologies, parasitic “estimates,” and a combination of constraints and automated layout features to prototype blocks that can be fully extracted and analyzed.
Leveraging a number of Virtuoso technologies
—including Schematic Editor, Analog Design Environment, Multi-Mode Simulation, Layout Suite, and rapid analog prototyping capabilities—the parasitic-aware design flow maximizes efficiency, decreases turnaround time, and enables a predictable design schedule. In-design manufacturing signoff and power analysis
The Cadence custom/analog flow enables design teams to confidently address manufacturing variability with new design-for-manufacturing (DFM) tools that automatically locate and fix potential DFM violations early in the design process and within their design layout environment. Such “in-design” capabilities ensure early and accurate manufacturing signoff, saving our customers time and money.
Traditional signoff requires designers to leave their layout window, run tools outside the database, view results in a third-party display, and then remember all the necessary fixes when they re-enter their layout environment. Cadence DFM signoff technology eliminates this error-prone and unsophisticated process—designers can see critical problems directly on their layout user-interface, automatically fix them, and refer to the fixes at any time during implementation.
The same in-design concept applies to the newly integrated Virtuoso Power System, which provides a signoff-accurate way to manage power and signal integrity issues—including IR drop and electromigration. With the Virtuoso 6.1.5 release, designers can access both DFM and power management capabilities in a single environment rather than switching back and forth between disparate software programs. New waveform technology and support for global teams
Cadence customers work on a 24-hr clock all over the globe. With Virtuoso 6.1.5, a variety of new publishing features facilitate the exchange of data and keep the project on schedule—users can maintain custom/analog design intent from specifications to tapeout, whether they’re on a single campus or dispersed around the world. Enhancements include automated constraint checking; a new design-rule editing engine designed to handle the complexity of advanced node rule sets; and an interactive short locator that guides designers through a find-and-fix process for difficult layout-versus-schematic errors.
The addition of the next-generation Virtuoso Accelerated Parallel Simulator
introduces a “distributed” mode. This offers customers more speed on single-core and multi-core machines, and delivers the power to harness multiple, multi-core machines for even the largest transient simulations. A completely upgraded waveform window technology has been tuned with our simulators to provide unmatched performance, and it eliminates the need to buy and integrate a third-party tool.
Feature stories archive »
- Custom/Analog Design Developments Meeting 65nm And Below Challenges - Gary Smith EDA, March 14, 2011
- Cadence Expands Virtuoso Custom/Analog Flow to Boost 20nm Productivity - Anne-Françoise PELE, EE Times, March 14, 2011
- Cadence Releases Custom/Analogue Flow - Steve Bush, Electronics Weekly, March 14, 2011
- Cadence Enhances Unified Custom/Analog Flow - Gabe Moretti, Gabe on EDA, March 14, 2011
- Cadence Design Systems Has Announced Major Enhancements to its Custom / Analog Flow, Said to Boost Productivity at Nodes Down to 20nm - Chris Shaw, New Electronics, March 14, 2011
- Cadence Enhances Unified Custom/Analog Flow to Boost Productivity at Nodes Down to 20nm - Pradeep Chakraborty, PC’s Semiconductor Blog, March 14, 2011
- 360 Degree enhanced unified custom/analog flow from Cadence - EE Herald, March, 15, 2011