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New Allegro 16.6 Release Accelerates Timing Closure on High-Speed PCB Interfaces by 30 to 50 Percent

Dedicated to improving constraint-driven PCB design flows and helping customers create products more efficiently, Cadence announces Allegro 16.6. This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.

“As chip designers are tasked with developing increasingly complex products, with tight time- to-market deadlines, having quick and easy access to design teams and resources both locally and globally creates a real competitive advantage,” says Simon Floyd, Director, Innovation and Product Lifecycle Management Solutions at Microsoft. “Cadence PCB design tools, integrated with SharePoint, provide a unique environment that promotes team collaboration, design creation and control, and significant productivity improvements.”

Enhanced miniaturization capabilities
Allegro 16.6 leverages the latest manufacturing advances to address the design requirements of ever-shrinking board sizes. The Miniaturization Option now allows users to embed components with dual-sided contacts and vertical components on the inner layers of a PCB. It also allows users to embed components in the dielectric of a two-layer PCB. These capabilities optimize board real estate.

Faster timing closure
Also new to Allegro 16.6 is auto-interactive delay tuning (AiDT) technology to accelerate timing-aware physical implementation. AiDT helps users meet timing constraints on advanced interfaces (such as DDR3) up to 50 percent faster. It allows users to rapidly adjust the timing of critical high-speed signals on an interface-by-interface basis or to apply it at the byte-lane‒level, thereby reducing PCB trace tuning from days to hours.

Improved ECAD and MCAD co-design
Allegro 16.6 offers a new flow that reduces unnecessary iterations between electrical CAD (ECAD) and mechanical CAD (MCAD) teams. PCB Editor now supports EDMD schema version 2.0 for incremental ECAD-MCAD co-design. This allows PCB designers and mechanical designers to accept/reject changes and capture comments on an object-by-object basis. Such a design collaboration environment translates into faster product creation.

The Cadence Allegro 16.6 release will be available Q4.


"We partnered with Cadence to optimize the Allegro environment’s use of OpenGL graphics on hardware equipped with NVIDIA Quadro GPUs. Allegro 16.6 improves our efficiency by removing the latency that was common on dynamic shape adherence to our design rules."
Greg Bodi
Director, Systems Design, NVIDIA
"Our leading ECP(C) technology meets customer needs for cost-effective miniaturization of PCBs. Cadence and AT&S have been partnering together for a number of years now, addressing our joint customers’ needs for advanced miniaturization techniques."
Mark Beesley
COO of Advanced Packaging, AT&S


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