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New Allegro 16.5 Technology

On May 23, 2011 Cadence will release the 16.5 version of its Allegro PCB and IC packaging technology, providing customers with new capabilities for a shorter, predictable, and convergent path to product creation. The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as:
  • Higher functional density with a constraint-driven flow for embedded components
  • Faster timing closure with new PCB interconnect design planning technology
  • Fewer physical prototype iterations with concurrent team design authoring
  • More efficient low-power design with integrated power delivery network analysis
  • A compliant and faster implementation path with package/board-aware SoC IP
  • Smoother collaboration among global teams with new SiP distributed co-design
  • Flexibility through “base plus options” configurations
System Realization
A major challenge PCB designers face is increasing the product’s functional density while reducing size and managing complexity. For more than 10 years, the Allegro environment has provided a constraint-driven PCB design methodology. With the 16.5 Allegro PCB Designer Miniaturization Option, design teams now have a constraint-driven methodology for creating/managing embedded packaged components. With this flow, PCB designers can employ advanced miniaturization techniques to reach new levels of functional density.

Increasing use of standards-based interfaces (DDR4, PCI Express 3.0) is making timing closure on PCBs extremely challenging. New Allegro PCB interconnect design planning technology uses Cadence-patented hierarchical abstraction coupled with semi-automatic approaches that leverage feedback from the route engine. This shortens the time to route dense, highly constrained designs and accelerates the path to timing closure.

The new concurrent team design authoring capability shortens the time to author virtual system logic and create design intent by leveraging the power and skill of a distributed engineering team. Multiple designers can work on the same design in a structured and controlled manner, eliminating the risk of unnecessary physical prototype iterations.

Accurate power delivery network (PDN) analysis enables more efficient low-power design. With Allegro PCB Designer in the 16.5 release, PDN analysis is integrated with the design environment. For the first time, engineers can perform PCB layout, signal integrity analysis, and PDN analysis in one common design/analysis environment. They can simulate-analyze-edit in rapid succession throughout the design cycle, optimize the PCB stack-up, and reach convergence on their low-power goals.

As more companies outsource designs and collaborate with partners in low-cost geographies, support for an OEM/ODM Joint Development Model (JDM) becomes important. Allegro Design Workbench is the only product available for team design and library/flow management that includes the capability to distribute, manage, and synchronize controlled component library subsets between partners, enabling JDM IP protection.

SoC Realization
Selecting and integrating SoC IP that works with package and board implementation has always been a challenge. Cadence technology enables engineers to create PCB implementation and consumable design-in IP that ensures swift, accurate, and optimized socket evaluations, without excessive evaluation cycles or silicon-vendor technical support. Starting with Allegro 16.5, Cadence provides package/board-aware SoC IP. The use of Cadence silicon IP that includes PCB design-in data enables silicon differentiation and faster time to socket. A package/board-aware DDR3 SoC IP methodology kit is also available to provide a compliant and fast implementation path from silicon IP to package and board.

Silicon Realization
Today, silicon design closure must include IC package and board. Cadence co-design technology facilitates communication of design intent among chip and package designers and geographically dispersed teams. This streamlines schedules and cost, enables more predictable design flows, and optimizes silicon performance. New Allegro 16.5 system-in-package (SiP) distributed co-design capability works with Encounter Digital Implementation System and the Virtuoso custom/analog design environment, enabling co-design across geographic and company boundaries for digital, analog, and mixed-signal silicon creation.

Flexible Product Configurations
The new Allegro 16.5 release will be available starting May 23. Customers can now purchase Allegro technology on-demand with “base plus options” configurations that can be tailored to their unique design challenges, allowing them to use exactly what they need when they need it.



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