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Achieve Electrically Correct-by-Construction Layout

Cadence® Virtuoso® Layout Suite for Electrically Aware Design (EAD) enables you to monitor electrical issues while you create your layout. By electrically analyzing, simulating, and verifying interconnect decisions in real time, you can enhance design team productivity, reducing your circuit design cycle by as much as 30 percent. What’s more, you can optimize chip performance and utilize less area for your custom ICs.

Key features in the solution include:
  • Built-in interconnect parasitic extraction engine that lets you perform real-time analysis and optimization
  • Electrical constraint management, which lets you set your constraints and monitor, in real time, whether the constraints are being met
  • Electromigration (EM) analysis, which highlights EM violations and provides recommendations to resolve them
  • Partial layout resimulation, which prevents errors from being buried deep in a packed layout
Since the solution is part of the Virtuoso platform, you can capture currents and voltages from simulations run in Virtuoso Analog Design Environment and seamlessly pass this electrical information into the layout environment. “EAD underscores our commitment to keep evolving our Virtuoso platform to ensure it meets the needs of the countless engineers who rely on it to tackle complex design challenges,” said Tom Beckley, senior vice president of R&D, custom IC and simulation, Silicon Realization Group, Cadence.



Cadence Virtuoso Layout Suite (VLS) for Electrically Aware Design (EAD) enables you to achieve electrically correct-by-construction layout and cut your system design cycle by 30%.


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