Virtuoso Platform to Be Used Across All Mainstream and Advanced Nodes
To address the increasing complexity associated with advanced node designs, TSMC has deployed the Cadence® Virtuoso® custom and analog design platform to design and verify its own cutting-edge IP across all mainstream and advanced nodes, including 16nm FinFET designs.
Additionally, TSMC will deliver fully qualified and high-quality native SKILL® process design kits (PDKs) to enable all the leading-edge features of the Virtuoso platform, providing the best user experience and highest level of accuracy.
So that you can fully maximize performance and quality of results, the new PDKs enable leading-edge features within the Virtuoso 12.1 platform, such as auto-alignment, automatic handling of complex rules during abutment, chaining devices, support of color-aware layout, and advanced routing. Key tools include Virtuoso Schematic Editor, Virtuoso Analog Design Environment, and Virtuoso Layout Suite XL and advanced GXL technologies.
“We have continued our major investments in advancing the Virtuoso platform to address the ever-mounting design challenges. We worked closely with TSMC and our customers to enhance and deliver on advanced node and mainstream design requirements. The high-quality native SKILL PDKs are key to powering up the Virtuoso methodologies to their full potential.”
Dr. Chi-Ping Hsu
Senior Vice President, Research and Development, Silicon Realization Group, Cadence
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