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Enabling Advanced Design, Technology, and Tooling

Through an ongoing, multi-year agreement, Cadence and TSMC will develop the design infrastructure for 16nm FinFET technology. The collaborative effort will target advanced-node designs for mobile, networking, servers, and FPGA applications.

Addressing the complete flow from design analysis through signoff, the companies will provide an infrastructure for the design of ultra-low power, high-performance chips. At advanced FinFET nodes, you’ll gain an infrastructure that supports the accurate electrical characteristics and parasitic models needed for successful design implementation.

“Producing the design infrastructure necessary for these types of complex, groundbreaking processes requires close collaboration between foundries and EDA technology innovators. In joining with TSMC, a leader in FinFET technology, Cadence brings unique technology innovations and expertise that will provide designers with the FinFET design capabilities they need to bring high-performance, power-efficient products to market.”

Chi-Ping Hsu, Senior Vice President, Silicon Realization Group, Cadence

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