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Accurately Measure Timing with 3X Less System Memory

Chip design—driven by increasingly sophisticated applications and shrinking process geometries—continues to get more complex. At the same time, traditional FastSPICE technologies are no longer effective in meeting the verification challenges found at advanced nodes. Cadence’s new Spectre® eXtensive Partitioning Simulator (XPS) fills a gap in simulation technology, providing capabilities that address increasing parasitics, low-power circuit structures, variation, and other advanced-node challenges.

With its unique partitioning technology and new FastSPICE algorithm, Spectre XPS supports higher capacity and up to 10X faster simulation throughput while requiring up to 3X less system memory. You’ll have the accurate timing analysis needed for advanced-node, low-power mobile applications. And you’ll be equipped to shorten simulation from weeks to just days.

Key Product Features
The Spectre XPS simulation solution delivers:
  • Event-driven, multi-rate simulation
  • Advanced model reduction technology
  • Advanced static and dynamic checking
Lower Support Costs, Faster Time to Production
Spectre XPS unites with the Spectre Circuit Simulator platform, supporting its methodologies and process design kits (PDKs). The complete Spectre infrastructure covers SPICE, advanced SPICE, RF, and FastSPICE. You can reuse models, stimulus, analysis, and your overall methodology, reducing support costs and accelerating your time to production.

Spectre XPS also integrates into the Cadence Virtuoso® Analog Design Environment for mixed-signal design, and into the Cadence Virtuoso Liberate MX memory characterization tool for SRAM memory characterization.
"As designs continue to grow in complexity and size, new simulation technologies are needed to address such issues as the timing impact of IR drop and power gating. The Spectre XPS FastSPICE simulator addresses these new challenges through next-generation algorithms that deliver the simulation accuracy and performance required to reduce the risks of developing cutting-edge differentiated designs."
Tom Beckley, Senior Vice President, Custom IC and PCB Group, Cadence

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