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Meet Your Active Power Goals with Cadence PCI Express Gen3 Controllers and PHY

With the newly announced Cadence® PCI Express (PCIe®) 3.0 controllers and PHY, you can decrease the energy consumption in power-sensitive datacenters and enterprise applications. A unique circuit calibration technique in the IP enables you to meet your aggressive active power goals, while advanced power and clock management capabilities reduce standby current by 100X.

“With datacenters responsible for two to three percent of worldwide energy consumption, advanced technology like our new PCIe IP can have a significant impact for our customers and end consumers,” said Martin Lund, senior vice president, SoC Realization Group at Cadence. “Leveraging Cadence’s many years of high-speed SerDes design, our new PCIe 3.0 controllers and PHY will help our customers reduce leakage power consumed by the PCIe interface from milliWatts to microWatts.”

The new PCIe IP supports x16 configuration, providing you with maximum performance along with virtualization support to service multi-threaded applications. With the additional support of the latest low-power PCIe L1 PM Substates engineering change notice (ECN) across all Cadence PCIe IP, Cadence can provide low power and high performance during peak operation, as well as system power savings during idle operation.

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