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Home > About Cadence > Newsroom > Cadence Articles > Interconnect Workbench: Your Answer to Better SoC Banwidth and Latency
Find and Fix Interconnect Problems Earlier in Your Design Cycle

Achieving SoC performance goals
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Without an accurate, quick way to assess interconnect performance, you risk encountering bandwidth and latency problems that can impact system-on-chip (SoC) performance and even lengthen time to market for your design. Until now, such a solution didn’t exist. Now, using the performance analysis capabilities of the Cadence® Interconnect Workbench, you have a graphical way to compare interconnect simulation runs.

Advanced SoCs are commonly built around multi-layered interconnect intellectual property (IP) blocks. These sophisticated interconnects are enabling new generations of low-power servers and high-performance mobile devices. They are also highly configurable, and even minor variations in their configuration can impact SoC performance.

Interconnect Workbench simplifies verification of interconnect data integrity and identifies performance bottlenecks before they get locked into silicon. The tool automatically generates Universal Verification Methodology- (UVM-) compliant performance and verification testbench code from ARM® CoreLink™ AMBA® Designer output. You can compare, side-by-side, the simulation runs of different interconnect configurations.

Key features include:
  • Performance GUI to help you debug system performance behaviors
  • Aggregated traffic data for pinpointing outlier transactions
  • Support for cycle-accurate performance-sensitivity analysis, so you can compare different implementation options and quality-of-service configurations
Interconnect Workbench works with Cadence Interconnect Validator, verification IP that verifies the correctness and completeness of data as it passes through the SoC.

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