X-Propagation Support, Two New Engines, and More
Ideal for meeting verification challenges for intellectual property (IP) block-to-chip and system-on-chip (SoC) implementations, the newest version of the Cadence® Incisive® functional verification platform sets a new standard for SoC verification performance and productivity.
The Incisive 13.2 platform is equipped with two new engines, additional automation that spans multiple technologies, and other new features that speed up verification closure. Among the features:
- An engine that improves formal analysis performance up to 20X
- A constraint engine that speeds Universal Verification Methodology (UVM) and SystemVerilog testbench simulation, and simulation acceleration with the Cadence Palladium® platform, by up to 10X
- IEEE 1647 e unit testing without simulation, which cuts testbench code debug time by 30%
- X-propagation support, which accelerates SoC reset and low-power simulations up to 5X
Read our article "Top 10 Ways to Automate Verification Using the Cadence Incisive 13.2 Platform
" to learn more about how the platform’s new key features work.
“Verification engineers are pressed for time and need strong verification performance. Incisive 13.2 delivers this, but also goes beyond raw clocks per second to encompass capabilities from formal apps, debug, and metric aggregation in order to speed verification closure,” noted Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence.
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