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Home > About Cadence > Newsroom > Cadence Articles > Cadence and ARM Tape Out First 64-bit ARM Cortex-A57 Processor on TSMC 16nm FinFET Process
Cadence and ARM® have partnered to implement the industry’s first 64-bit ARM Cortex™-A57 processor on TSMC’s 16nm FinFET manufacturing process. The test chip was implemented with the complete Cadence® RTL-to-signoff flow, the Cadence Virtuoso® custom design platform, ARM Artisan® standard-cell libraries, and TSMC’s memory macros.

The close, ongoing collaboration has resulted in several innovations and co-optimization of process, intellectual property (IP), and design tools. The Cadence custom, digital, and signoff products resolve key design challenges at the 16nm FinFET process, including new design rules, double patterning across more layers, and increased complexity of resistance models for interconnects and vias.

“This major milestone was challenging on all fronts, requiring engineers from ARM, Cadence, and TSMC to work as a unified team. Our combined efforts and commitment to innovation will enable our customers to adopt the next generation of IP, process, and design technology for designing high-performance, low-power SoCs.”

Dr. Chi-Ping Hsu, Senior Vice President of R&D, Silicon Realization Group, Cadence

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