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Home > About Cadence > Newsroom > Cadence Articles > New Cadence Analog IP Family Delivers Fastest Performance at 28nm
Cadence's complete family of analog IP addresses applications from data converters to monitors, timing, and power

Leading-edge designs need high-performance analog IP. Cadence provides high-performance analog front ends (AFEs) and data converters to power the latest radio and optical interfaces.
  • IP family delivers up to 10X faster conversion rate than available competing IP solutions
  • High-performance cores enable next-generation applications, such as WiGig (802.11ad)
  • Broad IP family offering for consumer, mobile, infrastructure, and industrial markets
The Cadence® 28nm analog IP family consists of a series of four easily integrated and highly testable IP solutions:
  • 7-bit 3GSPS dual analog-to-digital converter (ADC) and digital-to-analog converter (DAC)
  • 11-bit 1.5GSPS dual ADC
  • 12-bit 2GSPS Dual DAC
  • The data converter IP cores can be easily combined to form a complete AFE
At 3GSPS, the 7-bit converters are 10X faster than existing 300MSPS competitive offerings. These high-speed converters uniquely meet the needs of developers working with emerging high-speed protocols such as WiGig (802.11ad), which runs on a 60GHz spectrum with potential data throughput up to 7Gbps.

Figure 1: IP9931 3GSPS ADC Figure 2: IP9934 3GSPS DAC

At 2GSPS, the 11-bit/12-bit converters address key applications in the wired/wireless communication, infrastructure, imaging, and software-defined radios.

The ADC IP cores use a successive approximation array (SAR) architecture, which produces extremely fast sample rates. High effective-number-of-bits (ENOB) values are achieved with a unique implementation and built-in background auto calibration, producing more accurate conversion and consistent performance. The Cadence IP includes features such as differential data inputs, reference and timing generator, internal offset correction, and voltage regulators for improved supply noise immunity.

The DAC IP cores use a current switching architecture and include a digital multiplexer and FIFO for easy integration into a SoC. The DACs include digital gain control and all required reference circuitry.

All the IP includes multi-level power-down modes for additional power savings, a built-in analog test bus for design testability, and single-ended CMOS or differential current-mode logic (CML) clock inputs for a flexible clock interface.

The Cadence IP provides matching dual channels for communication systems where these are desired, simplifying implementation and reducing risk, as well as a standard CMOS process target for easy manufacturing.

The Cadence Analog IP family is available today in the 28nm process as well as a variety of other mature process nodes. In addition, Cadence offers a comprehensive offering of IPs in 28nm, including everything from interface, memory, peripheral, Tensilica® processor, and other analog IPs to provide customers a complete 28nm IP offering. Cadence offers over 250 analog IPs in various process technologies including sensors, timing, and power IPs. Over 100 million chips have been shipped with Cadence analog IP.
"The ability to easily integrate the Cadence Data Converter IP in advanced process nodes eliminates the need to go ‘off-chip’ and allows designers to take full advantage of the system benefits of integrating both the digital and analog content into a single complex SoC. This translates to longer battery life, smaller thermal profile, and lower overall system cost."
Martin Lund, Senior Vice President of the Cadence IP Group
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