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Home > About Cadence > Newsroom > Cadence Articles > Cadence Sets the Global Standard in VIP for AMBA-Based SoCs
Cadence Sets the Global Standard in VIP for AMBA-Based SoCs

Customers around the world choose Cadence Verification IP (VIP) to verify SoCs based on ARM® AMBA® protocols. Mature and proven on thousands of production designs, Cadence VIP for AMBA reduces verification time from months to weeks across a wide range of applications. It supports both traditional and emerging AMBA protocols, providing customers such as CEVA, Faraday, and HiSilicon with a comprehensive and flexible solution for SoC development.

Developers of the latest multi-core mobile SoCs employing cache-coherent fabrics use Cadence VIP to verify compliance with ARM’s AMBA 4 AXI™ Coherency Extensions (ACE™) specification. Cadence VIP for ACE, along with our new Interconnect Validator, were used by ARM’s leading customers even before the ACE specification was publicly released.

To date, dozens of cache-coherent designs have been verified using the Cadence solution. One such design success is with HiSilicon, a leading provider of ASICs for communications networks and digital media. “Delivering advanced multi-core ARM SoCs to our customers requires leading IC design technologies,” explains Ting Lei, HiSilicon’s Director of Cloud Computing. “The Cadence VIP for AXI4 and ACE enables us to quickly and efficiently deliver bug-free SoC designs.”

Cadence also offers the industry’s most trusted VIP for ARM’s traditional AXI™, AHB™, and APB™ protocols. Our solution includes verification plans, coverage models, test suites, and automatic protocol checks to ensure that design bugs are quickly detected and corrected. Verification plans integrate with the debug environment to show how collected coverage maps to the protocol specification’s requirements.

Cadence VIP seamlessly supports all major simulators and testbench languages including SystemVerilog and e. Supported methodologies include the industry-standard Universal Verification Methodology (UVM) as well as pre-cursor methodologies OVM and VMM.

Verification of today’s advanced designs requires more than simulation alone. To that end, Cadence provides Assertion-Based VIP for formal analysis and Accelerated VIP for simulation acceleration using our Palladium® XP hardware accelerator. Using Accelerated VIP, customers like Samsung achieve verification throughput hundreds of times faster than logic simulation.

"As the complexity of ARM partners’ designs increases year after year, successfully verifying the performance of the SoCs has become a critical imperative. The comprehensive Cadence verification IP solution for AMBA protocols has enabled our mutual customers to address this challenge while incorporating the latest ARM technology."
Joe Convey, Director of Design Enablement, ARM
"We adopt the Cadence VIP solution for its maturity, full feature set, and support. With the adoption, Faraday can provide customers with comprehensive SoC and IP-level verification coverage."
Ken Liao, R&D Associate VP, Faraday
"Delivering advanced multi-core ARM SoCs to our customers requires leading IC design technologies. The Cadence VIP for AXI4 and ACE enables us to quickly and efficiently deliver bug-free SoC designs."
Ting Lei, Director of Cloud Computing, HiSilicon
"ARM’s partnership with Cadence helps customers achieve continued success as they roll out next-generation designs incorporating our most advanced AMBA specifications such as AXI4 and AXI Coherency Extensions (ACE)."
Joe Convey, Director of Design Enablement, ARM
"The flexible Cadence VIP for AXI gives us the ability to adapt it to our unique application and exhaustively verify the bus interconnects. This cut our verification effort from 6 months to 3 weeks."
Richard Kingston, Director of Marketing & Investor Relations, CEVA Inc.


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ACE R&D part 2: Acceleration
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ACE AEs part 1: Simulation
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