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Cadence 3D-Aware Methodology and Tool Support

To stay ahead of market demand for smaller gadgets with longer battery life and richer multimedia features, engineering teams are looking to advanced process nodes and new design approaches. An increasingly popular solution is using three-dimensional integrated circuits (3D-ICs) with through-silicon vias (TSVs).

3D-ICs with TSVs offer compelling power, perfor¬mance, and form factor advantages, especially for the mobile market. And because 3D-IC technology allows you to stack die from different process nodes, it does not require that you move all system components to a single advanced node—you can keep analog/RF circuitry at a mature process node on a separate die. This capability can greatly reduce development costs and speed time to market.

But to harvest all the benefits of 3D-IC technology, engineering teams need “3D-aware” design tools that work harmoniously. They also need a new, end-to-end methodology that drives design, implementation, and verification across digital, analog, and packaging domains.

Cadence offers a unified 3D-IC Solution to help you achieve cutting-edge, cost-effective results. For the last six years we have worked closely with customers and ecosystem partners, such as TSMC, to develop a comprehensive 3D-IC methodology that spans planning, implementation, test, analysis, verification, and ultimately signoff.

The Cadence 3D-IC Solution supports:
  • 3D-aware implementation (placement, optimization, and routing) of heterogeneous die, with seamless data transfer between custom and digital domains
  • 3D-aware verification (extraction and analysis) at both chip and system levels for optimal timing, power, and thermal characteristics
  • 3D-aware design for test (DFT) and automatic test pattern generation (ATPG)
  • IC/package co-design and system analysis with 3D visualization
  • Design and verification IP for Wide I/O (controller and PHY) to enable faster memory access
  • Enhanced system-level exploration
The Cadence 3D-IC Solution is validated on eight test chips and one production chip. To make 3D-ICs with TSVs more mainstream and adoptable, Cadence is committed to expanding the support ecosystem through ongoing technological innovation and partner collaboration.

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