will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.
Home > About Cadence > Newsroom > Cadence Articles > Cadence, ARM, and Samsung Tapeout Industry's First Cortex-A-Based 14nm/FinFET Chip
FinFET-Ready Ecosystem Drives Innovation

The 14nm FinFET process is the new frontier of electronics design. A 14nm FinFET design combines the optimized area and performance boost required for next-generation platforms while also ensuring very low power dissipation. A breakthrough in process technology, it is ideal for the mobile device market.

But 14nm/FinFET poses a number of design, implementation, and manufacturing challenges—new design rules, double-patterning requirements, complex routing, 3D parasitic extraction, and power network analysis. It requires a new methodology, process design kits, physical IP, and an ecosystem of support from foundry, IP, and EDA companies.

Through close collaboration, Cadence, ARM, and Samsung have taped out the industry’s first Cortex-A based bulk CMOS 14nm FinFET test chip. Built on the high-performance ARM® Cortex™-A7 processor and designed with the comprehensive Cadence® Encounter® RTL-to-signoff flow, it is the first such type of chip to effectively utilize the Samsung 14nm FinFET process. ARM used Cadence Virtuoso® tools to develop the 14nm FinFET libraries. The Cadence flow delivers a complete methodology for custom and digital cell design, place-and-route, signoff extraction, timing, and power analysis at 14nm with FinFETs.

Highlighting the value of global collaboration, the project was completed in just two months, with RTL developed in Hsinchu, physical implementation performed in and standard cells designed in Austin, memories in San Jose, and fabrication in Seoul. The announcement is a leap forward in process validation to help customers adopt 14nm/FinFET and develop cutting-edge SoCs for future mobile devices.

Scaling Down from MOSFET to FinFET
The metal-oxide semiconductor field-effect transistor (MOSFET) has been the most widely used transistor in both digital and analog circuits. But in the mobile device era—with more mixed-signal circuitry, ultra-fast microprocessors, and the need for chips to do far more than ever before all while consuming less power—engineers have had to continually advance MOSFET technology. High-κ dielectric + metal gate combinations. And now the FinFET.

The FinFET is a multi-gate non-planar transistor (3D and more compact), which allows gate-length scaling to resume per Moore’s law. In a FinFET, the FET gate wraps around three sides of the transistor's elevated channel, or "fin." Multiple fins can be used to provide more current. As a result, designers have much more control over current than with planar transistors. And since the 3-D fin structure greatly reduces substrate capacitance, leakage power is reduced significantly.

14nm FinFET Design and Implementation Methodology
14nm/FinFET presents a unique set of challenges. In addition to FinFET-based DRC and double-patterning colorization requirements for implementation, FinFETs also require advanced timing, extraction, and power analysis to be characterized correctly. Furthermore, 14nm FinFET designs are expected to be larger in scale, and have more aggressive power, performance, and area targets.

The Cadence flow used to design the breakthrough test chip addresses these challenges, from RTL to signoff. Virtuoso tools are used to design the standard cell libraries and custom IP, reading in 14nm design rules through an open and integrated database. Then, using 14nm FinFET rules, Encounter Digital Implementation (EDI) System performs automated place-and-route. Double-patterning correctness is integrated in the flow during placement, optimization, and routing using EDI System with NanoRoute® technology.

For 14nm FinFET signoff, Cadence QRC Extraction takes into account the non-uniform current and voltage characteristics of FinFETs, using advanced transistor-level extraction and modeling techniques. It also generates multi-value SPEF data to model mask-shift variations for double patterning.

Encounter Timing System uses more accurate timing models and multi-value SPEF data to perform signoff timing analysis, while Encounter Power System performs power signoff. Accurate timing and power signoff is critical at 14nm, and central to the Cadence flow.

FinFET-Ready Ecosystem
Early collaboration among process, library, and methodology developers is extremely important for mainstream adoption of the 14nm node and FinFET technology. Cadence is committed to working with electronics ecosystem leaders like ARM and Samsung. Together, we’re enabling new process technologies and paving the way for innovation in the mobile device market.

“Cadence’s advanced node design flow, coupled with our collaboration with ARM and Samsung, is essential to semiconductor companies as they move to designing for a 14-nanometer FinFET process. Our common goal is to enable our customers to reap the benefits and competitive advantages of designing at the most advanced technologies.”
Dr. Chi-Ping Hsu
Sr. Vice President, R&D, Silicon Realization Group, Cadence
“End consumers are driving the need for better, faster, more connected devices. Our collaboration with ARM and Cadence allows us to innovate quickly as Samsung develops this new process technology for mobile multimedia applications.”
Dr. Kyu-Myung Choi
Sr. Vice President, System LSI Infrastructure Design Center, Device Solutions, Samsung
“Taping out ARM’s most energy-efficient applications processor on Samsung’s advanced low-power manufacturing process was achieved through the combination of leading-edge technology and R&D excellence, as well as a deep and early collaboration with Samsung and Cadence.”
Dipesh Patel
Vice President and General Manager, Physical IP Division, ARM

Press releases: Technologies: Solutions:
Feature stories archive »