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Home > About Cadence > Newsroom > Cadence Articles > Cadence Support for 16nm FinFET Digital and Custom/Analog Flows and 3D-IC
Cadence/TSMC Collaboration Ensures Your Tools and Process Work Seamlessly Together

TSMC and Cadence deliver two new flows: digital and custom/analog flows for the 16nm FinFET process and the latest 3D-IC reference flow with true 3D stacking.

Cadence’s custom/analog, digital, and signoff tools have implemented methodology innovations that allow you to achieve TSMC’s16nm FinFET process benefits of higher performance, lower power consumption, and smaller area. The TSMC 16nm Custom Design Reference Flow incorporates the use of optimized 16nm native SKILL process design kits (PDKs) to enable an innovative FinFET custom design flow by applying a number of fins at every design stage, together with a robust set of productivity-enhancing Virtuoso capabilities for leading custom/analog design.

You can use the latest 3D-IC reference flow with true 3D stacking to seek power/performance advances without moving to tiny geometries. The flow, validated on a memory-on-logic design with a 3D stack based on a Wide I/O interface, enables multiple die integration with higher performance, reduced power consumption, and a smaller form factor.
“As more electronics companies turn to 16nm FinFET technology for power savings and performance advantages, it’s important they know their design tools and manufacturing process have been tested to ensure they work seamlessly together. The inclusion of these Cadence technologies in TSMC Reference Flows helps our customers meet their time-to-market goals and stay competitive in advanced technology design.”
Suk Lee
TSMC Senior Director, Design Infrastructure Marketing Division, TSMC
“3D-IC represents a dramatic new approach to product integration. It provides a new dimension to Moore’s Law and requires a deep collaboration for a seamless enablement offering. This latest reference flow demonstrates real progress in our work with TSMC to make 3D chips not just viable, but an attractive option for addressing chip complexity.”
Dr. Chi-Ping Hsu
Chief Strategy Officer and Senior Vice President of Digital and Signoff Group, Cadence

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