First Integrated Tool Certification for TSMC 20SoC Process Technology
A production-ready set of Cadence® design tools is the first integrated tool certification for TSMC’s 20SoC process technology. Certified through the design of an ARM® Cortex™-A9 processor, the tool chain enables you to enjoy the speed, power, and area benefits of the 20nm node.
Several Cadence system-on-chip (SoC) development tools have also achieved version 0.1 of design rule manual (DRM) and SPICE model tool certification for TSMC’s 16nm FinFET process. This milestone means that you can start developing designs and taking advantage of lower power and higher performance benefits for next-generation mobile platforms at advanced nodes.
“Vertical collaboration at the earliest possible stages of solution development is key to delivering co-optimized solutions,” said Dr. Chi-Ping Hsu, senior vice president of research and development, Silicon Realization Group at Cadence. “TSMC’s certification of Cadence tools for 16nm FinFET and 20nm design underscores our joint commitment to working with our customers to help ensure their success.”
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