Home > About Cadence > Newsroom > Cadence Articles > Cadence Delivers New Encounter Digital Implementation System for Design Success at 20nm and Below
Full-flow GigaOpt and natively integrated CCOpt technologies boost productivity, ease design closure, and accelerate time to market

Cadence delivers a much improved digital flow with the latest release of its industry-leading Encounter® Digital Implementation (EDI) System, providing full production silicon-proven capabilities and readiness for 20nm design. It includes leading foundry certifications, comprehensive coverage for handling increased design rule and double-patterning requirements from prototyping to final routing, and signoff optimization.

In addition, version 13.1 offers support for early adopters of 14nm and 16nm FinFET process technologies. GigaOpt is now the default multithreaded optimization technology pervasive through the implementation flow, from pre-route to clock design to post-route optimization. Clock Concurrent Optimization (CCOpt) is now natively integrated, utilizing common extraction, delay calculation, timing, placement, routing and powerful optimization engines, to deliver improved quality of results, run-times, and signoff-correlated complex clock implementations.

Fine tuned for high-performance designs at advanced nodes
Modern high-performance microprocessors enable SoC designs for a wide range of exciting applications in high-end mobile computing, digital home and gaming, low-power servers, and wireless/networking infrastructure. SoC designers desiring to exploit the full potential of such high-performance processors need considerable implementation expertise, design tools, and thorough knowledge of advanced process nodes (28/20nm and 16/14nm FinFET) to achieve an optimal balance between power, performance and area (PPA).

EDI System, with its core multi-threaded GigaOpt and CCOpt technologies, synergistically combines to deliver unprecedented improvements to total-negative-slack (TNS), worst-negative-slack (WNS), density, and run-times. EDI System is bolstered by key new components: ultra-fast block-level floorplan/place-and-route feasibility analysis, FlexModel abstraction for 100M+ instance designs, route-driven optimization, new track assignment that uniquely targets DRC and SI/timing closure, while simultaneously reducing area and leakage power, and signoff optimization. Bringing these EDI System technologies to bear, Cadence has jointly developed state-of-the-art RTL-to-signoff flows with industry-leading silicon IP vendors for high-performance 64- and 32-bit control-plane and data-plane processors at advanced nodes. In addition, Cadence has delivered readily deployable foundation flows to help SoC designers achieve superior PPA with increased productivity and faster design closure.

Full 20nm certification and preparedness for 14nm/16nm FinFET process technologies
Designers migrating to 20nm and below need to account for new and important wire characteristics, timing closure, design size, and manufacturing considerations. EDI System has been fully certified by leading foundries such as TSMC, Samsung, and GLOBALFOUNDRIES for production designs on 20nm technologies. EDI System supports 20-nanometer rules, a patented double-patterning technology for correct-by-construction placement and routing, and GigaOpt optimization for achieving better quality of silicon with a shorter turnaround time.

The importance of FinFETs as the next frontier of evolution in process technology cannot be stressed enough. A 14/16nm FinFET process can potentially offer a 40-50% performance increase or a 50% power reduction compared to a 28nm process. Adopting such bleeding-edge technologies into a chip flow requires tremendous effort to make designs feasible and economically viable. EDI System has geared up to support the complexities associated with FinFET technologies as exemplified by several unique and successful test-chip tape-outs with leading foundries such as IBM, Samsung and TSMC.

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