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03 Dec 2014 Stanford's Jim Plummer to be awarded IEEE Founders Medal - Stanford Report

25 Nov 2014 Megachips to Launch DSP-Based Sensor Fusion IC - EE Times23 Nov 2014 Acceleration homes in on power issues - Tech Design Forum21 Nov 2014 Over the FR4 and Through the Woods - EE Journal21 Nov 2014 Make the Move from Module-Based Mixed-Signal Verification to UVM - Electronic Design Europe20 Nov 2014 Hybrid Verification: The Only Way Forward - Semiconductor Engineering20 Nov 2014 Conflicting Needs For IoT Edge Designs - Semiconductor Engineering20 Nov 2014 Making Models Interoperable - Semiconductor Engineering20 Nov 2014 The Internet Of Cores - Semiconductor Engineering20 Nov 2014 The Next Big Shift In Verification - Semiconductor Engineering20 Nov 2014 Measuring Verification Accuracy - Semiconductor Engineering19 Nov 2014 How To Speed Signoff Extraction By 5X With Next-Generation Extraction Tool - Semiconductor Engineering19 Nov 2014 Q&A: Moving Towards Use Case and Software-Driven Verification - Design & Reuse14 Nov 2014 Photoresist Problems Ahead - Semiconductor Engineering14 Nov 2014 Cadence Professorship Endowed at Stanford - PCB Design 00713 Nov 2014 Semiconductor IP Information Flow! - SemiWiki12 Nov 2014 IP-SoC 2014 - Top Class Presentations11 Nov 2014 How Sonics Uses Jasper Formal Verification - SemiWiki11 Nov 2014 Using Cadence PVS for Signoff at TowerJazz - SemiWiki10 Nov 2014 More Things Are Critical Systems - Semiconductor Engineering08 Nov 2014 India Semiconductor Consumption and Make In India Initiative - Electronics Maker07 Nov 2014 What’s Working For Power Verification - Semiconductor Engineering07 Nov 2014 Industry Collaboration Starts - Semiconductor Engineering06 Nov 2014 Keeping Up With The Productivity Challenge - Semiconductor Engineering06 Nov 2014 Are More Processor Cores Better? - Semiconductor Engineering06 Nov 2014 Designing For Energy Efficiency - Semiconductor Engineering06 Nov 2014 Another Tool In The Bag - Semiconductor Engineering06 Nov 2014 Virtual Prototyping Takes Off - Semiconductor Engineering06 Nov 2014 Semiconductor Safety - SemiWiki06 Nov 2014 The Multicore Processing Conundrum - Semiconductor Engineering05 Nov 2014 Mixed-Signal Summit Panel: Why IoT Design is Harder Than it Looks - Design & Reuse04 Nov 2014 High Power Tools for Low Power - Systems Design Engineering04 Nov 2014 In-Design DFM Signoff for 14nm FinFET Designs - SemiWiki03 Nov 2014 Linley Conference: The Processor Dilemma for IoT and Mobile - Design & Reuse01 Nov 2014 What Presentations to Attend During IP-SoC 2014? - SemiWiki

31 Oct 2014 Pushing the Performance Boundaries of ARM Cortex-M Processors for Future Embedded Design - Systems Design Engineering31 Oct 2014 Top 10 Lessons Learned about IP Management - Chip Estimate30 Oct 2014 Are Models Holding Back New Methodologies? - Semiconductor Engineering29 Oct 2014 Cadence Functional Safety Verification Solution Reduces ISO 26262 Preparation Effort by up to 50 Percent - John Day’s Automotive Electronics29 Oct 2014 Verification IP supports 25G Ethernet specification - Electronic Specifier29 Oct 2014 Verification IP for 3D memory structures - EDN Network29 Oct 2014 Verification suite aids 26262 compliance - EDN Network29 Oct 2014 Cadence Mixed Signal Technology Forum - SemiWiki28 Oct 2014 Verification IP supports popular 3D memory standards - Electronic Specifier28 Oct 2014 Cadence tool automates library creation of analog macros - Tech Design Forum28 Oct 2014 20-times faster, full Spice accuracy, from Cadence’s AMS simulation - EDN Europe28 Oct 2014 Cadence prepares automotive designers for ISO26262 - New Electronics25 Oct 2014 Cadence releases IP for 3D memory - Electronics Weekly24 Oct 2014 Cadence extends verification suite to aid 26262 compliance - EDN Europe24 Oct 2014 Software eases ISO26262 implementation - EE Times Europe23 Oct 2014 Redefining A System…And Why It Matters - Semiconductor Engineering23 Oct 2014 Cadence Lands Biggest Deal in Years - Electronics 36023 Oct 2014 Advanced Nodes Drive Changing EDA Requirements - Semiconductor Engineering23 Oct 2014 System Design Enabling Surround Computing - Semiconductor Engineering23 Oct 2014 Are Models Holding Back New Methodologies - Semiconductor Engineering22 Oct 2014 Top 10 Ways To Automate Verification - Semiconductor Engineering19 Oct 2014 MIPI Soundwire IP Sounds Innovative - SemiWiki18 Oct 2014 Placement optimizations push power and clock on Cortex-M7 project - Tech Design Forum15 Oct 2014 IPC-2581 Adoption Update - PCB Design 00714 Oct 2014 Choosing the right A/D converter architecture and IP to meet the latest high speed wireless standards - New Electronics11 Oct 2014 TSMC ♥ Cadence! - SemiWiki10 Oct 2014 Will There Be A DDR5? - Semiconductor Engineering09 Oct 2014 Energy Boost For Power Standards - Semiconductor Engineering09 Oct 2014 Memory Directions Uncertain - Semiconductor Engineering09 Oct 2014 The Democratization Of System Design - Semiconductor Engineering09 Oct 2014 Optimizing Analog For Power At Advanced Nodes - Semiconductor Engineering07 Oct 2014 Not Far from Formal to Success - EDA Café03 Oct 2014 Cadence and ARM expand system-on-chip design collaboration - Connecting Industry03 Oct 2014 Cadence Digital and Custom/Analog Tools Achieve TSMC Certification for 16FF+ Process - Electronic Specifier02 Oct 2014 Securing The IoT - Semiconductor Engineering01 Oct 2014 More Than Moore - Semiconductor Engineering

30 Sep 2014 Cadence has IP, tools for 16-nm FinFET Plus node; looks onwards to 10nm - EDN Europe26 Sep 2014 The Real Numbers: Redefining NRE - Semiconductor Engineering25 Sep 2014 IoT Demands Correct By Construction Assembly - Semiconductor Engineering25 Sep 2014 Challenges Increase for IP At Advanced Nodes - Semiconductor Engineering25 Sep 2014 How To Cut Verification Costs For IoT - Semiconductor Engineering25 Sep 2014 Time To Market Concerns Worsen - Semiconductor Engineering25 Sep 2014 Productivity And The IoT - Semiconductor Engineering22 Sep 2014 Executive Insight: Lip-Bu Tan - Semiconductor Engineering22 Sep 2014 Cadence's Rowen Forecasts Processor Design Split - Design & Reuse18 Sep 2014 EDA Vendors Prepare For 7nm - Semiconductor Engineering17 Sep 2014 New flows needed for the 'insects of the SoC world' - Tech Design Forum17 Sep 2014 Mammal EDA and insect EDA - Electronics Weekly11 Sep 2014 Where Is Gene Roddenberry When You Need Him? - Semiconductor Engineering11 Sep 2014 IoT Brings Low Power To Forefront - Semiconductor Engineering11 Sep 2014 Are We Headed For A Power Wall? - Semiconductor Engineering11 Sep 2014 Making Chips Run Faster - Semiconductor Engineering11 Sep 2014 Design For IoT - Semiconductor Engineering11 Sep 2014 Limiters To The Internet Of Things - Semiconductor Engineering10 Sep 2014 TSMC selects Cadence library characterisation tool setting - Electronic Specifier05 Sep 2014 Profiles in Design: Brad Brim - EDN04 Sep 2014 IoT Growing Pains - Semiconductor Engineering

29 Aug 2014 Complexity of Mixed-signal Designs - Systems Design Engineering28 Aug 2014 Faster Extraction from Cadence - EE Journal23 Aug 2014 Cadence white paper helps you selecting what come after DDR4 - SemiWiki22 Aug 2014 Cadence and Reverse Debugging - SemiWiki22 Aug 2014 Fixing Functional Coverage - Semiconductor Engineering22 Aug 2014 Verification Made Easy with Memory Models - EE Journal21 Aug 2014 Different Approaches Emerge For Stacking Die - Semiconductor Engineering21 Aug 2014 More Than Moore - Semiconductor Engineering21 Aug 2014 The Changing IP Ecosystem - Semiconductor Engineering21 Aug 2014 Looking For The Next Big Thing - Semiconductor Engineering20 Aug 2014 Bug-Busting Technology Takes to the Road - Business Weekly19 Aug 2014 VLSI design trend 2014: Silicon hungry software to silicon for app - EE Herald17 Aug 2014 Innovating in system of systems: Lip Bu-Tan - Pradeep's Point15 Aug 2014 Cadence Completes Power Signoff Solution with Voltus-Fi - SemiWiki15 Aug 2014 Signoff Intensity On The Rise - Semiconductor Engineering14 Aug 2014 A Deeper Insight into Quantus QRC Extraction Solution - SemiWiki11 Aug 2014 Latest IPC-2581 Revision Gaining Widespread Appeal - Printed Circuit Design & Fab07 Aug 2014 Established Nodes Getting New Attention - Semiconductor Engineering07 Aug 2014 Making Software Better - Semiconductor Engineering07 Aug 2014 When Will 2.5D Cut Costs? - Semiconductor Engineering07 Aug 2014 Test Becomes Power-Aware - Semiconductor Engineering07 Aug 2014 Three ways to improve PCB design productivity and predictability with hierarchical interface-aware design capability - Embedded Computing Design07 Aug 2014 Dealing with parasitic-extraction challenges in finFETs and advanced nodes - Tech Design Forum06 Aug 2014 Transistor-level EMIR sol'n offers speedier design closure - EE Times India05 Aug 2014 EDA software delivers power integrity analysis for IC designs - EDN Europe05 Aug 2014 Power integrity solution delivers fast path to design closure - EE Times Europe04 Aug 2014 Designing For Security - Semiconductor Engineering03 Aug 2014 Cadence Quantus solution meets 16nm FinFET challenges - Pradeep's Point

31 Jul 2014 Planning PCB, Package, and Die Together - EE Journal30 Jul 2014 Chip design has morphed into system design - Electronics Weekly30 Jul 2014 Cadence expands its OrCAD portfolio - New Electronics29 Jul 2014 OrCAD PCB software adds data management and library tools - EDN28 Jul 2014 IoT--Is security impeding development of the IoT? Frank Schirrmeister talks about security and his three components of IoT - EDA Café28 Jul 2014 FD-SOI: 20nm Performance at 28nm Cost - SemiWiki27 Jul 2014 Cadence adds 3 new products to its ORCAD PCB design software - EE Herald25 Jul 2014 Tool targets the acceleration of mainstream PCB design - Electronic Specifier25 Jul 2014 The Week In Review: Design - Semiconductor Engineering24 Jul 2014 High-Level Gaps Emerge - Semiconductor Engineering24 Jul 2014 New Winners And Losers - Semiconductor Engineering24 Jul 2014 IP Integration Challenges Rising - Semiconductor Engineering24 Jul 2014 EDA's Hedge Plays - Semiconductor Engineering24 Jul 2014 Reversing Course, With A Twist - Semiconductor Engineering24 Jul 2014 Data and documentation focus for Orcad PCB additions - Tech Design Forum24 Jul 2014 Cadence unveils OrCAD solutions for PCB design process - EE Times India24 Jul 2014 New OrCAD PCB Technologies - PCBDESIGN00724 Jul 2014 Cadence Targets Emerging Design Challenges - PCBDESIGN00723 Jul 2014 Prototyping system boosts capacity and performance - Engineer Live23 Jul 2014 PCB tools target emerging design challenges - Softei22 Jul 2014 FPGA-Prototyping Simplified - EE Journal21 Jul 2014 Protyping tool adds to Palladium suite - Softei21 Jul 2014 Cadence unveils FPGA-based rapid prototyping platform - EE Times India21 Jul 2014 Cadence Results: Good but Palladium under Price Pressure - SemiWiki21 Jul 2014 The Internet of Everything--What are we really facing? - EDA Café18 Jul 2014 Large-system rapid prototyping, software development & low-power verification from Cadence - EDN Europe18 Jul 2014 Prototyping tool speeds time-to-market - Electronic Specifier17 Jul 2014 DFM And Multipatterning - Semiconductor Engineering17 Jul 2014 Palladium's Little Brother Protium - SemiWiki17 Jul 2014 Cadence brings FPGA prototyping and emulation into sync - Tech Design Forum17 Jul 2014 Partitioning tool eases multi-FPGA-based prototyping - EE Times Europe16 Jul 2014 RC extraction tool certified for 16nm FinFET designs - EE Times India16 Jul 2014 Cadence delivers RC extraction solution - EE Times India16 Jul 2014 RC extraction tool accelerates design signoff - Electronics Specifier16 Jul 2014 Cut design flow parasitic extraction time in half - Electronics Specifier16 Jul 2014 CADENCE boosts the performance of parastic extraction tool - ELE Times15 Jul 2014 Cadence addresses extraction issues of finfets and double-patterning - Electronics Weekly15 Jul 2014 Extraction tool for faster FinFETs - Radio-Electronics.com11 Jul 2014 Semiconductor leaders talk about industry's future�Part 1 - EE Times India10 Jul 2014 Raising The Abstraction Of Power: Trends - Semiconductor Engineering10 Jul 2014 Supporting LP In New Process Nodes - Semiconductor Engineering10 Jul 2014 28nm FinFETs? - Semiconductor Engineering09 Jul 2014 We need Electronics Development Fund: Cadence MD on Budget 2014 expectations - CIOL09 Jul 2014 What's Next? Semiconductor Leaders Speak, Part 1 - EBN08 Jul 2014 Focusing coverage for system-level integration - Tech Design Forum08 Jul 2014 28mn design taped out using timing signoff tool - Electronic Specifier07 Jul 2014 Mixing it up - Electronic Specifier07 Jul 2014 Cadence and QNX Announce Tensilica HiFi Audio/Voice DSP Application for In-Car Active Noise Control - John Day Automotive Electronics03 Jul 2014 Semiconductor Industry Outlook: Enormous Opportunity, Says Jaswinder Ahuja - Design and Reuse03 Jul 2014 Hybrid execution - the next step in the evolution of hardware-software co-development - EDN Europe02 Jul 2014 So Easy To Learn VIP Integration into UVM Environment - SemiWiki02 Jul 2014 Trends in the mobile memory world - Techonline India01 Jul 2014 PCI Express 4 specification just released for PCI-SIG DevCon - SemiWiki

30 Jun 2014 DAC 2014 - Panel: FinFET IC Design Poses No Roadblocks, but Lots of Details26 Jun 2014 Semiconductor R&D Crisis Ahead? - Semiconductor Engineering26 Jun 2014 3 Challenges Of Delivering Configurable Semiconductor IP - Semiconductor Engineering26 Jun 2014 Can EDA Keep Growing? - Semiconductor Engineering26 Jun 2014 Moore's Law Tail No Longer Wagging The Dog - Semiconductor Engineering26 Jun 2014 Asynchronous Is Mostly Academic - Semiconductor Engineering26 Jun 2014 Everyone Is A Programmer - Semiconductor Engineering25 Jun 2014 Cadence, QNX team up for in-car active noise control - EE Times India20 Jun 2014 Cadence Offers Production Proven USB 3.0 Host Controller IP - Electronic Specifier20 Jun 2014 Virtuoso Layout Suite for EAD Adopted By ON Semiconductor - Electronic Specifier19 Jun 2014 Cadence closes Jasper deal - Radio-Electronics.com19 Jun 2014 Ethernet: The Highway For Automotive Electronics? - Semiconductor Engineering19 Jun 2014 DFM And Multipatterning - Semiconductor Engineering19 Jun 2014 Five Disruptive Test Technologies - Semiconductor Engineering17 Jun 2014 Cadence completes acquisition of Jasper Design Automation - Solid State Technology17 Jun 2014 2014 DAC Interviews - EDA Café16 Jun 2014 New Uses For Emulation - Semiconductor Engineering13 Jun 2014 Do SoCs Need Earthquake Insurance? - Semiconductor Engineering12 Jun 2014 S-L Power Modeling Gains Steam - Semiconductor Engineering12 Jun 2014 Computer Vision's Enormous Challenges Ahead - Semiconductor Engineering10 Jun 2014 Digital Designers Grapple with Analog Mixed Signal Designs - Chip Design Magazine10 Jun 2014 Logical chain-based clock implementation - EDN05 Jun 2014 Updated EDA tools supporting Intel's 14nm Tri-Gate foundry - EE Herald03 Jun 2014 Hybrid execution - the next step in the evolution of hardware-software co-development - EDN03 Jun 2014 Ceaseless Field Test for Safety Critical Devices - SemiWiki02 Jun 2014 Deeper Dive – Is IP reuse good or bad? - System Design Engineering

29 May 2014 New Uses For Emulation - Semiconductor Engineering28 May 2014 USB 3.0 Host Controller IP, as used in industry standard Compliance Program - EDN Europe28 May 2014 Cadence and ARM expand collaboration for 64-bit processor designs - Connecting Industry26 May 2014 EDA and the cloud - Embedded Computing Design23 May 2014 Cadence solution promises rapid die-package interconnect planning - Radio-Electronics22 May 2014 CSR Selects Cadence Palladium XP Platform for Development of ARM-based Automotive Infotainment Systems - EDA Café22 May 2014 The Assertion Conundrum - Semiconductor Engineering22 May 2014 When And Where To Use Virtual Prototypes - Semiconductor Engineering21 May 2014 Panel Discussion: File Transfer Formats - PCB Design 00721 May 2014 Cadence IP solutions available on 28nm FD-SOI process - Electronic Specifier21 May 2014 Industry's first verification IP for PCI Express 4.0 - Electronic Specifier21 May 2014 Cadence Extends Spectre XPS to Support Mixed-Signal Designs - Connecting Industry21 May 2014 Don't Miss Cadence's In-Depth Tech Demos at DAC 2014 - EDA Café20 May 2014 CDNLive: ARM signs 64-bit core deal with Cadence - Electronics Weekly20 May 2014 CDNLive: Cadence SPICE simulator for transistor-level mixed-signal - Electronics Weekly20 May 2014 Multicore fastSpice extends reach - Tech Design Forum20 May 2014 Cadence signs with ARM for core optimizations - Tech Design Forum20 May 2014 Jasper at DAC - SemiWiki20 May 2014 Cadence Spectre XPS supports mixed signal designs - Radio-Electronics19 May 2014 Cadence Announces Availability of IP Solutions on 28nm FD-SOI Process - Electronics-Sourcing19 May 2014 Cadence System & Verification Newsletter May 2014 - EDA Café19 May 2014 Cadence DDR4 PHY IP developed on 16nm FinFET process - EE Times India17 May 2014 Cadence ports IP and qualifies tools for 28nm FD-SOI - Tech Design Forum16 May 2014 Availability of IP solutions on 28nm FD-SOI process - Connecting Industry15 May 2014 FDSOI: Is Cadence, Not Samsung, the Tipping Point? - Design and Reuse12 May 2014 Design Your Career On A Tiny Wafer - Electronics For U08 May 2014 Can HLS Be Trusted? - Semiconductor Engineering08 May 2014 Improving LP Verification Efficiency - Semiconductor Engineering08 May 2014 IP To Meet 2.5D Requirements - Semiconductor Engineering08 May 2014 Pointing Fingers, Often In The Wrong Direction - Semiconductor Engineering06 May 2014 Sound software ported to a licensable IP DSP core - Electronic Specifier02 May 2014 Cadence adds 3D sound to Tensilica IP - Electronics Weekly02 May 2014 Cadence adds 3D sound software to HiFi DSPs -

30 Apr 2014 Deeper Dive - System Design Engineering30 Apr 2014 The Shaughnessy Report: Out With the Old, In With the New? - PCB Design29 Apr 2014 ARM Utilizes the Cadence Library Characterization Solution for Advanced Node Foundation IP Development - TMCnet24 Apr 2014 Does Formal Have You Covered? - Semiconductor Engineering24 Apr 2014 Extending UVM To Analog - Semiconductor Engineering24 Apr 2014 What Are EDA's Big Three Thinking? - Semiconductor Engineering24 Apr 2014 Graphing Toward Standardization - Semiconductor Engineering24 Apr 2014 Efficiency Metrics Get Fuzzy - Semiconductor Engineering23 Apr 2014 Cadence to buy Jasper Design Automation for $170M - EE Times India23 Apr 2014 Cadence breaks into top four in semi IP core ranking - EE Times Europe23 Apr 2014 Cadence grows formal verification profile with Jasper DA buyout - EDN Europe23 Apr 2014 Custom processor tool wins $2.8m backing - EE Times Europe23 Apr 2014 Cadence buys Jasper for $170m - Radio-Electronics.com23 Apr 2014 Analyst: Cadence enters top four in semi IP core ranking - EE Times India22 Apr 2014 Cadence Gobbles Up Jasper - Semiconductor Engineering22 Apr 2014 Cadence to acquire Jasper Design Automation for $170m - Electronic Specifier22 Apr 2014 Cadence to expand formal portfolio with Jasper buy - Tech Design Forum22 Apr 2014 Cadence agrees Jasper Design acquisition - Electronics Weekly22 Apr 2014 Cadence looks to expand Verification Solution with acquisition of Jasper Design Automation - Components in Electronics22 Apr 2014 Cadence to Acquire Jasper - EE Times22 Apr 2014 Cadence Acquires Jasper - SemiWiki22 Apr 2014 Cadence snaps up Jasper Design Automation - Electronic Specifier22 Apr 2014 EDA company Cadence designs a future beyond chip simulation - 451 Research21 Apr 2014 Cadence digital and custom/analog tools achieve TSMC V1.0 DRM certification for 16nm FinFET process - CIOL21 Apr 2014 Cadence News By Design: New IP and VIP Solutions, Website, and More - Apr 2014 - EDA Café17 Apr 2014 Does Processor IP still get the Lion�s share in 2013? - SemiWiki17 Apr 2014 Cadence: Plan verification to avoid mistakes! - electronicsforu.com15 Apr 2014 Mentor and Cadence tools certified for TSMC 16nm FinFETs - Electronics Weekly14 Apr 2014 Cadence: Plan verification to avoid mistakes! - Pradeep Chakraborty's Point!10 Apr 2014 Power Moves Up To First Place - Semiconductor Engineering10 Apr 2014 Architecting For Efficiency - Semiconductor Engineering09 Apr 2014 High Level Synthesis: Significant Differences Remain - Semiconductor Engineering09 Apr 2014 Addressing MCU Mixed Signal Design Challenges - SemiWiki03 Apr 2014 Exposed by Tools - EE Journal01 Apr 2014 PCB Designing for Engineers - Electronics For U

31 Mar 2014 Big Shift In SoC Verification - Semiconductor Engineering31 Mar 2014 Automating Analog Verification in Virtuoso - SemiWiki27 Mar 2014 Formal Is Set To Overtake Simulation - Semiconductor Engineering27 Mar 2014 Distortion Effects Prevail In RF Design - Semiconductor Engineering27 Mar 2014 How Much Will That Chip Cost? - Semiconductor Engineering27 Mar 2014 EDA Shapes Its Future - Semiconductor Engineering27 Mar 2014 The Great Shift To The Left - Semiconductor Engineering20 Mar 2014 Enabling Test Portability With Graphs - Semiconductor Engineering20 Mar 2014 Yamaha reduces leakage power by 50 percent in mobile chip using Cadence low-power solution - CIOL20 Mar 2014 Cadence Incisive Specman Elite testbench reduces verification time for Sharp by 50 percent - CIOL20 Mar 2014 ARM, Cadence and the Internet of Things - SemiWiki19 Mar 2014 Yamaha Reduces Power Leakage by Half in Its Mobile Chips - Mobility Techzone18 Mar 2014 Board Revolution - EE Journal17 Mar 2014 Big Shift In SoC Verification - Semiconductor Engineering16 Mar 2014 Cadence is all about Semiconductor IP! - SemiWiki14 Mar 2014 A Tale of Two Tools - EE Journal14 Mar 2014 ARM-based design verification is crucial, says Cadence - Electronics Weekly13 Mar 2014 Know What To Look For - Semiconductor Engineering13 Mar 2014 High Level Synthesis Grows Up - Semiconductor Engineering13 Mar 2014 The Next Bigger Things - Semiconductor Engineering13 Mar 2014 Cadence and ARM BFF - SemiWiki12 Mar 2014 System Level Power Budgeting - Chip Design Magazine12 Mar 2014 Pointing Fingers In Verification - Semiconductor Engineering11 Mar 2014 5 Keys For Optimizing SoC Latency and Bandwidth - Chip Design Magazine10 Mar 2014 Execs to talk 16nm chips design - SmartBrief06 Mar 2014 CDNLive: Verification Challenges Driving Innovation - EE Times06 Mar 2014 Faster timing closure of high-speed PCB interface designs - EDN Europe06 Mar 2014 Big Shift In SoC Verification - Semiconductor Engineering05 Mar 2014 Automating PCB Timing Closure, Saving Up to 67% - SemiWiki05 Mar 2014 Verification Moves to Database - EE Journal05 Mar 2014 Visual timing tool focuses on high-speed PCB signals - Tech Design Forum05 Mar 2014 New Cadence TimingVision Technology Speeds PCB Interface Design - EE Times04 Mar 2014 Reducing And Optimizing Power - Chip Design Magazine04 Mar 2014 Cadence Announces Allegro TimingVision Environment - Printed Circuit Design & Fab Magazine04 Mar 2014 What I Didn't Know about Electronic Design Automation - SemiWiki

27 Feb 2014 Is Verification at a Crossroads? - Semiconductor Engineering27 Feb 2014 10 Must-Knows About Virtual Prototypes - Semiconductor Engineering27 Feb 2014 Abstractions: The Good, Bad and Ugly - Semiconductor Engineering27 Feb 2014 EDA Hungers for Growth - Semiconductor Engineering26 Feb 2014 Effective hardware-software co-design for automotive systems - Embedded Computing Design25 Feb 2014 Cadence introduces Incisive vManager solution - Financial News24 Feb 2014 Voice activation sol'n cuts power dissipation in mobiles - EE Times India24 Feb 2014 SoC Functional Verification Planning and Management Goes Big - SemiWiki24 Feb 2014 Cadence uses SQL to boost verification manager capacity - Tech Design Forum19 Feb 2014 Cadence offers always-on sensor fusion platform - EE Times Europe17 Feb 2014 Cadence buys high speed interface IP assets from TranSwitch - EE Times India14 Feb 2014 The industry's first Android technology for a licensed DSP - Electronic Specifier13 Feb 2014 Heat Problems Grow With FinFETs, 3D-ICs - Semiconductor Engineering13 Feb 2014 Power Reduction Through Sequential Optimization - Semiconductor Engineering13 Feb 2014 Microsoft uses Cadence Tensilica processors in Xbox One - Radio-Electronics.com13 Feb 2014 Microsoft uses configurable processor in Xbox One - Electronics Weekly11 Feb 2014 Elevating Their Game - EE Journal10 Feb 2014 Cadence acquisition enhances high-level synthesis offering - Components in Electronics09 Feb 2014 Cadence to acquire Forte Design Systems - EE Herald07 Feb 2014 Higher Ground - EE Journal06 Feb 2014 Cadence buys Forte Design Systems - EE Times Europe05 Feb 2014 DDR4 PHY IP reaches 2667Mbps at 28nm: 3200Mbps next? - EE Times Europe05 Feb 2014 Cadence to buy Forte and build out HLS offering - Tech Design Forum05 Feb 2014 Cadence to buy Forte - Semiconductor Engineering03 Feb 2014 High-Definition Sound Expansion Now Licensable on Tensilica HiFi DSP Cores from Cadence - SOCcentral

31 Jan 2014 Multi-Fabric Planning for Efficient PCB Design - Printed Circuit Design & Fab30 Jan 2014 Patents Under Scrutiny - Semiconductor Engineering30 Jan 2014 The Growing Verification Challenge - Semiconductor Engineering30 Jan 2014 How to Speed Up Verification - Semiconductor Engineering30 Jan 2014 The Road Ahead for 2014: Development Tools - Semiconductor Engineering28 Jan 2014 CDNLive World Tour - SemiWiki27 Jan 2014 Experts At The Table: Yield And Reliability Issues With Integrating IP - Semiconductor Engineering22 Jan 2014 It Takes a Team to Assure Power Integrity - PCB Design22 Jan 2014 What is the Current State of ESL Tools? - Chip Design Magazine21 Jan 2014 New products offer a lot of potential: Cadence India MD - The Hindu Business Line21 Jan 2014 Mixed Signal and Microcontrollers Enable IoT - Chip Design Magazine16 Jan 2014 Power's Impact On Hierarchy Modification - Semiconductor Engineering16 Jan 2014 Mostly Accurate Computing - Semiconductor Engineering16 Jan 2014 Performance Still Trumps Power - Semiconductor Engineering16 Jan 2014 Which IP Is Better? - Semiconductor Engineering16 Jan 2014 "India is a bit like Taiwan in semicon" - The Times of India15 Jan 2014 C-to-Silicon compiler used to speed video codec design - EDN15 Jan 2014 Cadence reduces Renensas' Design and verification time by 70 percent - Connecting Industry14 Jan 2014 Cadence Compiler speeds Renesas IP development - Radio-Electronics.com14 Jan 2014 Cadence gets Incisive to meet verification challenge - Electronics Weekly14 Jan 2014 Cadence updates Incisive with formal, CRV, wreal additions - Tech Design Forum08 Jan 2014 Experts At The Table: Yield And Reliability Issues With Integrating IP - Semiconductor Engineering08 Jan 2014 Cadence to add Fraunhofer's MPEG AAC codecs to its HiFi DSPs - EE Times India07 Jan 2014 Cadence licenses MPEG AAC codecs from Fraunhofer IIS - Electronic Specifier