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December

28 Dec 2012 Cadence 3D Methodology - SemiWiki24 Dec 2012 ARM, Cadence tape out 14nm FinFET test chip - EE Times19 Dec 2012 Executive Outlook - System-Level Design Community19 Dec 2012 Hybrid Execution And Software-Driven Verification Will Emerge In 2013 - Electronic Design18 Dec 2012 Looking Back At 2012 - System-Level Design Community12 Dec 2012 A look back on 2012: Business successes - EE Times11 Dec 2012 Smashing Through the Mobile Device Memory Bottleneck - ChipEstimate.com11 Dec 2012 Finfets take chips through geometry barrier - Electronics Weekly06 Dec 2012 'Challenges in designing mobile devices' - EE Times India06 Dec 2012 How to Close Timing with Hundreds of Multi-Mode/Multi-Corner Views - EE Journal06 Dec 2012 LP Design And Verification - Low-Power High Performance Engineering Community06 Dec 2012 Hardware Simulator Performance Scaling To Meet Advanced Node SoC Verification Requirements - Low-Power High Performance Engineering Community05 Dec 2012 Building Energy-Efficient ICs from the Ground Up - SOCcentral03 Dec 2012 3D ICs with TSVs: Design Challenges and Requirements - SOCcentral03 Dec 2012 Electrically-aware design improves analog/mixed-signal productivity - SOCcentral
 
November

30 Nov 2012 Mantra to drive New Generation of Semiconductors - Silicon India29 Nov 2012 Taming The Challenges Of 20nm Custom/Analog Design - System-Level Design Community28 Nov 2012 Cadence donates multi-patterned lithography technology - EE Times28 Nov 2012 The verification engineer's stethoscope - ChipEstimate28 Nov 2012 The Agony Of Choice - System-Level Design Community27 Nov 2012 New Cadence IP fuels automotive ethernet designs - EE Times22 Nov 2012 Shun outsourcing mentality, design own electronic devices: Lip-Bu Tan, Cadence Design - The Economic Times16 Nov 2012 Experts At The Table: Obstacles In Low-Power Design - Low-Power High Performance Engineering Community12 Nov 2012 Cadence sets the Global Standards in VIP for AMBA based SoC - SemiWiki09 Nov 2012 We see lot of start-ups coming up in India - EE Times07 Nov 2012 Many Of Today's Design Challenges Are Interdependent: Cadence - EFY Times03 Nov 2012 Electromigration (EM) with an Electrically-Aware IC Design Flow - SemiWiki02 Nov 2012 Cadence, IBM push SOI FinFET design to 14-nm - EE Times
 
October

31 Oct 2012 Cadence reveals tapeout of 14-nm test-chip with ARM processor and IBM FinFET process technology - EE Times Europe30 Oct 2012 Verifying low-power intent in mixed-signal design - Tech Design Forum30 Oct 2012 IBM, ARM and Cadence tapeout first 14nm finfet processor - Electronics Weekly30 Oct 2012 IBM Tapes Out 14nm ARM Processor on Cadence Flow - SemiWiki30 Oct 2012 New growth drivers empower electronic design automation - Components in Electronics30 Oct 2012 The Power Wall: Are we scaling it or is it just getting higher? - Low-Power Design29 Oct 2012 Electrically-aware design improves analog/mixed-signal productivity - EE Times29 Oct 2012 Electrically-aware design improves analog/mixed-signal productivity - EE Times29 Oct 2012 Big 3 Executive Interview - Lip-Bu Tan, CEO, Cadence Design Systems - EDA Tech Channel26 Oct 2012 How to Verify ARM ACE Coherent Interconnects with UVM verification IP - Test & Measurement World26 Oct 2012 In-Design Signoff Avoids Iterations and Accelerates Time to Tapeout - Chip Design26 Oct 2012 Cadence Accomplishes Verification Projects for Major Customers - InfoTech Spotlight26 Oct 2012 In-Design Signoff Avoids Iterations and Accelerates Time to Tapeout - Chip Design26 Oct 2012 Cadence Accomplishes Verification Projects for Major Customers - InfoTech Spotlight26 Oct 2012 An AMS Reference Flow for Power Management Designs - SemiWiki25 Oct 2012 Cadence Design Systems Q3 Profit Rises - NASDAQ25 Oct 2012 Cadence Verification IP Significantly Reduces Verification Turnaround Time for ARM AMBA 4 Protocols - Electronic Specifier25 Oct 2012 ‘Known unknowns’ and the Cadence take on verification IP - Tech Design Forum23 Oct 2012 Cadence SiP technologies are optimized to work with Allegro Package Designer for hand-held consumer electronics market - EE Times Europe23 Oct 2012 Cadence SiP technologies are optimized to work with Allegro Package Designer for hand-held consumer electronics market - EE Times Europe23 Oct 2012 The Complexity Of System Development And Verification - System-Level Design Community19 Oct 2012 Understanding 28-nm SoC Design With ARM-Based Cores - Electronic Design19 Oct 2012 Understanding 28-nm SoC Design With ARM-Based Cores - Electronic Design15 Oct 2012 TSMC Validates Cadence 3D-IC Technology for Its CoWoS(TM) Reference Flow - Gabe on EDA12 Oct 2012 3D packaging takes a key step forward as TSMC tapes out CoWoS chips - EE Times Europe11 Oct 2012 New verification debugger offers significant productivity improvements - Components in Electronics11 Oct 2012 Experts at the Table: Black Belt Power Management - Part 2 - Low-Power High Performance Engineering Community11 Oct 2012 Experts at the Table: Black Belt Power Management-Part 2 - Low-Power High Performance Engineering Community11 Oct 2012 Experts at the Table: Black Belt Power Management - Low-Power High Performance Engineering Community10 Oct 2012 Lip-Bu Tan bullish on Indian chip industry - EE Times03 Oct 2012 Honouring a VC pioneer - Business Times01 Oct 2012 Mixed-signal SOC verification using analog behavioral models - EDNN Europe
 
September

27 Sep 2012 Cadence Introduces OrCAD v16.6 PCB Design Solution - EDA Blog26 Sep 2012 Cadence announces next release of Allegro PCB tool - Electronics Weekly26 Sep 2012 Cadence releases OrCAD 16.6 PCB design solution, boosts PSpice performance by up to 20 percent - EE Times Europe26 Sep 2012 Video: Overview of Mixed-Signal Design Methodologies - Low-Power Design Videos26 Sep 2012 Cadence Releases OrCAD 16.6, Boosts PSpice Performance - Gabe on EDA26 Sep 2012 Cadence Design Systems Debuts Allegro v16.6 Printed Circuit Board - EDA Blog25 Sep 2012 Cadence Allegro Uses Microsoft SharePoint - Gabe on EDA25 Sep 2012 Mixed-Signals: Tribulations of Combining Analog and Digital Design - Low-Power Design25 Sep 2012 Cadence announces Allegro 16.6 - EE Times21 Sep 2012 Unified, Concurrent Mixed-Signal Methodology - EDN21 Sep 2012 Cadence Mixed Signal Technology Summit - SemiWiki18 Sep 2012 Integration of semiconductor IP and compatibility by Cadence - Electronics Weekly14 Sep 2012 Cadence September News: strong IP and VIP focus (Synopsys/Cadence chess game continues) - SemiWiki13 Sep 2012 Experts at the Table: Black Belt Power Management - Part 1 - Low-Power High Performance Engineering Community13 Sep 2012 Experts at the Table: Black Belt Power Management - Low-Power High Performance Engineering Community12 Sep 2012 Book excerpt: Mixed-signal methodology guide - EE Times11 Sep 2012 How real number modelling is easing the analogue simulation challenge - New Electronics07 Sep 2012 Sending Mixed Signals - EE Journal04 Sep 2012 TSMC produces first Cadence DDR4 PHY on 28nm - Electronics Weekly04 Sep 2012 Cadence says 28-nm DDR4 IP proven on TSMC process - EE Times02 Sep 2012 A Brief History of Cadence Design Systems - SemiWiki
 
August

30 Aug 2012 Employ analog behavioral models for mixed-signal SOC verification - EDN Asia30 Aug 2012 Arm signs multi-year deal to optimise SoCs - Embedded News27 Aug 2012 In-Design Signoff Avoids Iterations and Accelerates Time to Tapeout - Chip Design23 Aug 2012 Cadence and MIET Celebrate Decade Of Partnership - EFY Times23 Aug 2012 Book Review: Mixed-Signal Methodology Guide - SemiWiki22 Aug 2012 Cadence at 20nm - SemiWiki21 Aug 2012 Mixed-signal SOC verification using analog behavioral models - EDN20 Aug 2012 MemCon 2012: when Cadence pick the best in Denali inheritance - SemiWiki14 Aug 2012 Cadence Publishes Book on Mixed-Signal Methodology - Gabe on EDA14 Aug 2012 Cadence Publishes Book On Mixed-Signal Methodology - EFY Times09 Aug 2012 ARM and Cadence pep up POPs - Electronics Weekly09 Aug 2012 ARM, Cadence tune support for processor design - EE Times09 Aug 2012 The Evolution Of Power Format Standards: A Cadence Viewpoint - Low-Power High Performance09 Aug 2012 ARM/Cadence collaboration boosts performance, power in ARM Cortex-A series based SoCs - EDN01 Aug 2012 Cadence Digital Flow - SemiWiki
 
July

27 Jul 2012 Parasitic-Aware Design Flow with Virtuoso - SemiWiki27 Jul 2012 Cadence Design Q2 Profit Rises - Quick Facts - NASDAQ26 Jul 2012 Cadence CEO sees design activity keeping pace - EE Times20 Jul 2012 Fujitsu taps Cadence signoff for ref design flow - EE Times India20 Jul 2012 Software Entrepreneur Helps Guide EDA Giant - JB's Circuit19 Jul 2012 Shorter, better and easier PCIe and NVM Express Verification flow with advanced technologies - SemiWiki17 Jul 2012 Cadence has added powerful capabilities to its PCI Express Verification IP including PIPE4 support - EDN16 Jul 2012 The Evolution of Power Format Standards - SoCcentral16 Jul 2012 Cadence enhances PCIe verification IP - EE Times India16 Jul 2012 Standard models for 3-D designs - EE Times16 Jul 2012 IC package prototyping methodology estimates feasibility and cost - EE Times15 Jul 2012 Cadence add new features to its PCI Express Verification IP - EE Herald14 Jul 2012 Indian government announces incentive package for electronics manufacturing - India Tech Online14 Jul 2012 Control dominated design - Forte Design Systems13 Jul 2012 Experts At The Table: Does 20nm Break System-Level Design? - System-Level Design Community12 Jul 2012 Cadence adds new capabilities to PCIe VIP including PIPE4 support to boost performance - EE Times Europe10 Jul 2012 Demand For EDA Engineers Increasing In India - EFY Times07 Jul 2012 Making 20nm Design Challenges Manageable - Chip Design Magazine03 Jul 2012 The Importance of Teamwork in Challenging Times - Silicon India03 Jul 2012 Cadence pays $80 million to buy signal integrity firm - EE Times02 Jul 2012 Cadence’s NVM Express: fruit from subsystem IP based strategy - SemiWiki01 Jul 2012 IC Package prototyping methodology estimates feasibility and cost - EE Times
 
June

28 Jun 2012 What You Need to Know to Establish a Digital Methodology for 28nm ARM Core-Based SoCs - IQ Magazine26 Jun 2012 How Firm Is Firmware? - System-Level Design Community20 Jun 2012 20nm Chips, 3D ICs, Low Power and Fast Tools Are Themes Of DAC 2012 - Electronics Design19 Jun 2012 The verification engineer's stethoscope - ChipEstimate18 Jun 2012 Leveraging software for faster system development - Drive for Innovation18 Jun 2012 A New 3D IC Approach - EE Journal17 Jun 2012 Cadence IP Strategy 2012 - SemiWiki14 Jun 2012 LP Macros 2 - Low-Power Engineering Community14 Jun 2012 What Color is Your Semiconductor IP Box? - JB's Circuit11 Jun 2012 Cadence/TSMC 3D - SemiWiki11 Jun 2012 ST using Cadence IC Tools with Module Generators at DAC - SemiWiki08 Jun 2012 Debugging at the hardware/software interface - Embedded Computing Design06 Jun 2012 TSMC and Cadence say 3D chips are now viable - Electronics Weekly06 Jun 2012 Collaboration at 28nm, 20nm and 14nm: IBM, Cadence, ARM, GLOBALFOUNDRIES, Samsung - SemiWiki05 Jun 2012 GloFo, TSMC report process tech progress - EE Times04 Jun 2012 20-nm test chip taped out by STMicro using Cadence tools - EE Herald04 Jun 2012 Cadence announces results of collaboration on 3D ICs - EE Times04 Jun 2012 Cadence aids ST's 20nm SoC test chip tape-out - EE Times India01 Jun 2012 Mixed-Signal Design Trends and Challenges - SOCcentral01 Jun 2012 What You Need to Know to Establish a Digital Methodology for 28nm ARM® Core-Based SoCs - IQ Magazine
 
May

31 May 2012 Cadence tools tape out 20-nm SoC test chip for ST - EE Times31 May 2012 What's The Difference Between SATA And NVMe? - Electronic Design31 May 2012 Orchestrating Change In IC Design - System-Level Design Community30 May 2012 DFI 3.1 supported by Cadence IP, includes LPDDR3 mobile memory - EE Herald22 May 2012 Interview with Michael McNamara - Vice President and General Manager of System Level Design at Cadence - EE Web Pulse22 May 2012 Endless Abstractions? - System-Level Design Community21 May 2012 Cadence CEO: EDA firms must innovate beyond software - EE Times Confidential18 May 2012 Cadence tips faster Spice coming soon - EE Times Europe18 May 2012 CDNLive! in Munich: Cadence is back on track! - SemiWiki17 May 2012 IPC-2581 Consortium Validates Bare Board Fab Data - Printed Circuit Design & FAB17 May 2012 IPC-2581 Consortium Validates Bare Board Fab Data - Printed Circuit Design & FAB15 May 2012 Cadence forges closer links between verification components - EE Times14 May 2012 Netronome reduces SoC power use with timing tricks - EE Times14 May 2012 Top 10 Tips for Success with Formal Analysis – Part 3 - EE Times09 May 2012 Cutting Edge Technologies Lead Nominations for American Technology Awards - Tech America Foundation06 May 2012 Forte Design Systems joins Cadence Connections program - EE Herald02 May 2012 Cadence Expands OrCAD Capture Marketplace - Gabe on EDA02 May 2012 TripleCheck IP validator from Cadence for IP compliance testing - EE Herald01 May 2012 How to Pick the Best Verification IP for Your Application - Chip Design Magazine
 
April

30 Apr 2012 Hierarchical methods for power intent specification - EETimes25 Apr 2012 2012 will be the year of power, again - Forte Design Systems25 Apr 2012 What would Joe do? Forte: Anchor Tenant in the ESL Mall - EDACafe19 Apr 2012 Sage words of advice from Forte Design Systems founder John Sanguinetti - EDN16 Apr 2012 Building Predictability Into Your Low-Power Design Flow - EE Times10 Apr 2012 Cadence has design flow for SMIC 40nm process - Electronics Weekly05 Apr 2012 "Selling System-Level Design" - System-Level Design Community03 Apr 2012 Opinion: What Comes After Power Intent Formats? - EE Times
 
March

30 Mar 2012 Cadence CEO Lip-Bu Tan Honored with Singapore Award - Chip Design Magazine30 Mar 2012 Extending the Metric-Driven Verification Methodology to TLM Featured - SOC Central28 Mar 2012 Slideshow: EE Times, EDN honor 2012 ACE Award winners - EE Times26 Mar 2012 Cadence supports development of the cloud - EE Times26 Mar 2012 Cadence introduces LPDDR3 memory IP solution - EE Times22 Mar 2012 Cadence unveils high-performance, low-power design IP to support LPDDR3 memory standard - EE Times Europe21 Mar 2012 Cadence expands Shanghai office and R&D center - Silicon Valley/San Jose Business Journal19 Mar 2012 Building a NAND flash controller with high-level synthesis - EE Times14 Mar 2012 What’s The Difference Between Software Development Platforms? - Electronic Design13 Mar 2012 Cadence TSMC, ARM call for more collaboration - EE Times13 Mar 2012 Alberto Sangiovanni-Vincentelli receives EDAA Lifetime Achievement Award - EE Times13 Mar 2012 CDNLive: the Keynotes - SemiWiki08 Mar 2012 Shoot the Engineer - Low-Power Engineering Community08 Mar 2012 Flexibility Vs. Portability In Emulation - Low-Power Engineering Community08 Mar 2012 Avoiding Chip Melt - Low-Power Engineering Community07 Mar 2012 Issues in IP - YouTube06 Mar 2012 Cadence reveals latest RTL to GDS flow - EE Times06 Mar 2012 Cadence offers design support to Australia's IC startups - EE Times05 Mar 2012 Cadence moves physical design software to 20-nm - EE Times02 Mar 2012 Cadence Says A Plus Is Complexity Curve - Investor's Business Daily01 Mar 2012 Komplexe Architekturen im Griff - EE24.net
 
February

13 Feb 2012 Power Intent Formats: Light at the End of the Tunnel? - EE Times09 Feb 2012 Virtual LP - Low-Power Engineering Community09 Feb 2012 Corporate citizenship challenge on Saturday - The Hindu06 Feb 2012 Good 2011 Results for Cadence - Gabe on EDA02 Feb 2012 Cadence a billion dollar company once again - EE Times01 Feb 2012 Cadence: Q4, Q1 View Beat; Year View Beats; Op Margin Improves - Barron's
 
January

30 Jan 2012 Top 10 Tips for Success with Formal Analysis – Part 2 - EE Times24 Jan 2012 The Art Of Double-Indirect Sales And Product Marketing - System-Level Design Community20 Jan 2012 Experts At The Table: Making Software More Energy-Efficient - Low-Power Engineering Community17 Jan 2012 New Book “Advanced Verification Topics” published by Cadence - EE Times12 Jan 2012 Experts At The Table: Making Software More Energy-Efficient - Low-Power Engineering Community12 Jan 2012 Rethinking Good Enough - Low-Power Engineering Community12 Jan 2012 The Next Big Challenge - Low-Power Engineering Community12 Jan 2012 When Worlds Collide: Saving Power In Communications Applications - Low-Power Engineering Community12 Jan 2012 Status Report: Power-Aware Design Flow - Low-Power Engineering Community12 Jan 2012 Making Software Better - Low-Power Engineering Community11 Jan 2012 Cadence expands proven NAND Flash design IP offering - Components in Electronics10 Jan 2012 Speeding up FLASH - EE Journal09 Jan 2012 Cadence Memory Controller and PHY IP Supports ONFI 3 - EDA Blog01 Jan 2012 The move to 3D die stacks drives interconnect consortia - DESIGN & PRODUCTS