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December

18 Dec 2011 Argyle Conversation: On Monday, November 28, 2011, Geoff Ribar, Senior Vice President and Chief Financial Officer, Cadence Design Systems, Inc., and Jason Redlus, Managing Partner, Argyle Executive Forum, discussed the value of trust and teamwork ... - Argyle Journal13 Dec 2011 Combining Prototyping Solutions to Solve Hardware/Software Integration Challenges - EE Times12 Dec 2011 Top 10 Tips for Success with Formal Analysis – Part 1 - EE Times09 Dec 2011 Use Transaction-Level Models to ensure hardware and software are in sync - Embedded Computing Design08 Dec 2011 Clock-Concurrent Optimization Reshapes IC Physical Design Flow - Chip Design Magazine01 Dec 2011 Accelerating PCB Power Delivery Network Design and Analysis - ECN
 
November

21 Nov 2011 Common Ground: Seeking Pin Assignment Balance in FPGA-Based Boards - Electronic Design21 Nov 2011 Prototypes: What is a prototype? - EE Times10 Nov 2011 How To Succeed At 20 nm - Electronic Design07 Nov 2011 Clock-Concurrent Optimization Reshapes IC Physical Design Flow - Chip Design Magazine
 
October

31 Oct 2011 Cadence names James Plummer to board of directors - Silicon Valley/San Jose Business Journal27 Oct 2011 Xilinx partners Cadence to introduce an Extensible Virtual Platform for software developers - EE Times Europe26 Oct 2011 Cadence CEO laments loss of VC in semis - EE Times25 Oct 2011 Samsung, Cadence tout collaboration on SoC - EE Times21 Oct 2011 Cadence CEO: Chip execs eye China, India - EE Times19 Oct 2011 Assertion-based verification in mixed-signal design - EE Times Europe18 Oct 2011 ARM, TSMC tape out 20-nm processor - EE Times18 Oct 2011 It takes three baby: Cadence, ARM and TSMC - EE Times18 Oct 2011 Cadence’s library characterization scripts now available in TSMC’s reference kit - EE Times Europe18 Oct 2011 ARM, TSMC Announce Smaller, Faster Version of Cortex A-15 Chip - PC Mag18 Oct 2011 ARM tapes out 'most advanced processor' on 20nm - Electronics Weekly17 Oct 2011 Assertion-based verification in mixed-signal design - EE Times11 Oct 2011 New Electronics roundtable: Industry collaboration the name of the game as comms links get faster - New Electronics
 
September

26 Sep 2011 Cadence releases additions to their Verification IP library - EE Times20 Sep 2011 Fujitsu chooses Cadence DFM for 28-nm - EE Times19 Sep 2011 High-speed memory controller spec released for DDR4 - EE Times14 Sep 2011 3D-IC Design: The Challenges of 2.5D versus 3D - EE Times01 Sep 2011 3DIC Challenges: Design with Test - Company Insight
 
August

25 Aug 2011 Will Wide I/O Reduce Cache? - System-Level Design Community25 Aug 2011 Wide I/O’s Impact On Memory - System-Level Design Community16 Aug 2011 Sunplus picks Cadence' transaction-level modeling flow for IC design - EE Herald09 Aug 2011 Get control of ARM system cache coherency with ACE verification - EE Times09 Aug 2011 Realizing the Promise of Electrically-Aware Custom IC Design - Electronic Design
 
July

28 Jul 2011 Solving Memory Subsystem Bottlenecks In 3D Stacks - System-Level Design Community12 Jul 2011 Cadence Acquires Power Specialist Azuro - EE Times12 Jul 2011 Samsung Confirms 20nm Design Infrastructure With Test Chip Tape-Out - Gabe on EDA01 Jul 2011 The Good, The Bad and The Timely: Bruggeman Takes On EDA - Electronic Engineering Journal
 
June

29 Jun 2011 Cadence Donates UVM World Website to Accellera - Gabe on EDA22 Jun 2011 Cadence Demos PCI Express 3.0 in Action - Xbit Laboratories15 Jun 2011 Verifying vital designs - Embedded Computing Design15 Jun 2011 Low power: The key issue for system integration in mobile devices - Embedded Computing Design09 Jun 2011 Verification IP for ARM's AMBA 4 Coherency Extensions protocol - EE Herald09 Jun 2011 Cadence has announced its products for TSMC's latest Reference Flow - EE Herald09 Jun 2011 Vishal Kapoor on SoC realization - EE Times09 Jun 2011 John Bruggeman Interview: Does the EDA industry need to be shaken up? - EE Times09 Jun 2011 How to survive DAC - EE Times07 Jun 2011 3-D IC design: New possibilities for the wireless market - EE Times06 Jun 2011 Cadence focuses industry on 20-nm chip design - PC's Semiconductors Blog03 Jun 2011 One-On-One: John Bruggeman - System-Level Design Community01 Jun 2011 Cadence Widens System-development Coverage, Revisits Hardware/Software Integration - EDN
 
May

31 May 2011 Can Cadence Take a Bite Out of the Apple Model? - The Motley Fool23 May 2011 Achieve your SoC Design Goals – Measure Twice, Cut Once! - EE Times11 May 2011 Cadence opens PCB EDA to Apple biz model - EE Times10 May 2011 Cadence acquires Altos Design Automation - EE Times09 May 2011 Cadence adds virtual models and FPGA prototyping to System Development Suite - EE Times08 May 2011 TSMC taps Cadence to provide DFM services - EE Times05 May 2011 Cadence adds virtual models and FPGA prototyping to System Development Suite - EDN04 May 2011 Cadence Rolls System-level Development Suite - EETimes04 May 2011 Two New Platforms for Systems Designers - SemiWiki.com04 May 2011 Cadence Takes Next Step on EDA360 Odyssey - New Electronics04 May 2011 Cadence takes next step on EDA360 odyssey - New Electronics
 
April

26 Apr 2011 Cadence Introduces Latest Version of Allegro - EE Times15 Apr 2011 Experts at the Table: EDA’s Next Challenges - System-Level Design Community14 Apr 2011 Experts at the Table: Verification at 28nm and Beyond - Low-Power Engineering Community14 Apr 2011 Verification at 28nm and Beyond - Low-Power Engineering Community11 Apr 2011 Cadence Rolls DDR4 IP for 'Final Frontier' - EE Times11 Apr 2011 Cadence Expands IP Offerings with DDR4 - EDN07 Apr 2011 Go Wide - EE Journal06 Apr 2011 Cadence Exec Discusses China Strategy - EE Times04 Apr 2011 Cadence Responds to the Synopsys FPGA Prototyping Book - EE Times04 Apr 2011 Cadence Announces Availability of DDR4 IP Solution - Gabe on EDA02 Apr 2011 The future is High-Level Synthesis - Forte Design Systems
 
March

31 Mar 2011 Cadence rolls wide I/O IP - EE Times31 Mar 2011 Experts at the Table: EDA’s Next Challenges - System-Level Design Community25 Mar 2011 Industry activity increases for analog EDA. Cadence updates Virtuoso - EDN15 Mar 2011 360 Degree enhanced unified custom/analog flow from Cadence - EE Herald15 Mar 2011 EDA Tools for 3D IC Design - Chip Design14 Mar 2011 Custom/Analog Design Developments Meeting 65nm And Below Challenges - Gary Smith EDA14 Mar 2011 Cadence Expands Virtuoso Custom/Analog Flow to Boost 20nm Productivity - Anne-Françoise PELE, EE Times14 Mar 2011 Cadence Releases Custom/Analogue Flow - Steve Bush, Electronics Weekly14 Mar 2011 Cadence Enhances Unified Custom/Analog Flow - Gabe Moretti, Gabe on EDA14 Mar 2011 Cadence Design Systems Has Announced Major Enhancements to its Custom / Analog Flow, Said to Boost Productivity at Nodes Down to 20nm - Chris Shaw, New Electronics14 Mar 2011 Cadence Enhances Unified Custom/Analog Flow to Boost Productivity at Nodes Down to 20nm - Pradeep Chakraborty, PC’s Semiconductor Blog
 
February

28 Feb 2011 Cadence Extends Verification IP Catalog - EETimes28 Feb 2011 Cadence Takes Another EDA360 Step - Gabe on EDA14 Feb 2011 DesignCon 2011 Videos: UVM and Silicon Realization, Tom Anderson, Cadence - EDA Cafe14 Feb 2011 DesignCon 2011 Videos: New 3D-IC Design Offering, Rahul Deokar, Cadence - EDA Café14 Feb 2011 DesignCon 2011 Videos: New PDN Analysis, Brad Griffin, Cadence - EDA Cafe14 Feb 2011 DesignCon 2011 Videos: New Power Architect, Hierarchical Low Power and Silicon Realization Flow, Rahul Deokar, Cadence - EDA Cafe14 Feb 2011 DesignCon 2011 Videos: Palladium System Verification, Michael Young, Cadence - EDA Cafe04 Feb 2011 Mercury News Interview: Lip-Bu Tan, President and CEO of Cadence Design Systems - San Jose Mercury News04 Feb 2011 EDA360 Evangelist Steve Leibson Discusses Chips, Packages, and Boards with EETimes' Brian Fuller at DesignCon 2011 - EDA360 Insider03 Feb 2011 End to End Flows Are Set to Reshape IC Design - New Electronics02 Feb 2011 Cadence Exec: EDA Needs 'Breakaway Value' - EE Times
 
January

31 Jan 2011 Cadence Rolls 28-nm Digital Design Flow - EE Times27 Jan 2011 Experts At The Table: Pain, Abstractions and ESL - System Level Design Community27 Jan 2011 Verification Moves To Forefront With Software And Methodology Focus - System Level Design Community26 Jan 2011 ESL Challenges - System Level Design Community21 Jan 2011 Spreadtrum tapes out 40-nm LP chip using Cadence Silicon Realization - EE Times17 Jan 2011 Warren Savage On: The Geometry of EDA 360 - Electronics Weekly14 Jan 2011 Experts At The Table: Assertion-Based Verification (Part 3) - System Level Design13 Jan 2011 Way forward for electronic design automation - The Hindu13 Jan 2011 Power Model Complexity Grows - Low Power Engineering Community07 Jan 2011 Experts At The Table: Assertion-Based Verification (Part 2) - System Level Design05 Jan 2011 EDN Names Cadence Allegro PCB Signal-Integrity tool to 2010 Hot 100 Products List - EDN