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December

16 Dec 2010 Experts At The Table: Assertion-Based Verification (Part 1) - System Level Design03 Dec 2010 Securing Intellectual Property - Processor02 Dec 2010 3D Stacked Die Create Unique Test Issues - Chip Design Magazine01 Dec 2010 Top-Down Approach Brings Fresh Challenges to the Design Process - Electronics Weekly
 
November

23 Nov 2010 A Few Rounds on EDA360 - IC Design & Verification Journal20 Nov 2010 Using IT Differently - Forbes10 Nov 2010 EDA 'co-opertition'—a new era or more lip service? - EE Times10 Nov 2010 John Bruggeman of Cadence on EDA360 at ARM Techcon 2010 - ARMDevices.net03 Nov 2010 A New Vision For the EDA Industry - New Electronics02 Nov 2010 Cadence Advocates Application-Driven Design - Low Power Design02 Nov 2010 Cadence Advocates Application-Driven Design - Donovan's Brain
 
October

29 Oct 2010 Who Does What - Low-Power Engineering Community27 Oct 2010 Cadence sketches out tools vision - EETimes Europe26 Oct 2010 UVM: Extending Standardization from Language to Methodology - Chip Design Magazine20 Oct 2010 Cadence, Xilinx form FPGA IP ecosystem microsite - EE Times13 Oct 2010 Close-up with John Bruggeman, senior VP-CMO, Cadence Design Systems - BtoB07 Oct 2010 Experts At The Table: Timing Constraints - Chip Design Magazine
 
September

28 Sep 2010 Cadence defines Cortex-A15 MPCore implementation methodology - EE Times08 Sep 2010 Andes Technology goes for Cadence's low power design tools - EE Herald01 Sep 2010 GlobalFoundries shows 28-nm AMS design kit - EE Times
 
August

09 Aug 2010 Reduce embedded SoC design cost & optimize IP integration - EE Times
 
July

30 Jul 2010 The Transformation of EDA - Chip Design Magazine24 Jul 2010 Cadence, Electronic Arts Lead Silicon Valley Companies in R&D Spending - Bloomberg22 Jul 2010 Cadence, ARM to develop ARM-optimized system realization solution - EE Times22 Jul 2010 What EDA360 Isn’t - System Level Design Community16 Jul 2010 Great Leap - Hindustan Times08 Jul 2010 Transaction-level modeling brings IP up to speed - Embedded Computing Design
 
June

28 Jun 2010 EDA360 – A Silicon System Vision we must Build Upon - NPD Management Corner25 Jun 2010 Heard at DAC: the Question on Everyone’s Mind - EDN16 Jun 2010 EDA Spins Into The Realm Of Software - Chip Design Magazine07 Jun 2010 Mike Gianfagna On EDA360 - EDA Café04 Jun 2010 The Road To DAC: One On One With Lip-Bu Tan - Chip Design Magazine04 Jun 2010 The Road To DAC: One On One With Lip-Bu Tan - System-Level Design Community
 
May

31 May 2010 What you need to know about EDA360 - Olivier Coudert's Blog25 May 2010 A new vision for EDA - New Electronics24 May 2010 Cadence, IBM team for 32-nm SOI IP - EDN19 May 2010 Cadence captivates delegates at CDNLive! EMEA with EDA360 vision - Pradeep’s Point14 May 2010 Cadence Move For Denali is Part of Wider Silicon IP Plan - Electronics Weekly14 May 2010 Cadence to Acquire Denali - PC's Semiconductor Blog13 May 2010 Cadence and Denali: Perhaps More Than Meets the Eye - Practical Chip Design13 May 2010 Why Cadence Is Buying Denali - Chip Design Magazine13 May 2010 Cadence Design to Buy Denali for $315M in Cash - Forbes11 May 2010 Do We Need Independent EDA Companies? - IC Design & Verification Journal10 May 2010 Using Unified Modeling Methods to Reduce Embedded Hardware/Software Development - Embedded.com07 May 2010 The Week In Review: May 7 - System-Level Design Community06 May 2010 Cadence Offers Silicon IP as Part of SoC Platform Initiative - Electronics Weekly06 May 2010 Cadence Unveils New Open Integration Platform - TMCnet.com06 May 2010 Cadence Accelerates SoC Realisation, Reduces Costs - EFYTimes.com06 May 2010 Cadence Integration Platform Enables SoC Design - Electronics Talk06 May 2010 Duolog’s Socrates chip integration hub supports EDA360 vision - Pradeep’s Point05 May 2010 Cadence Launches Open Integration Platform - Gabe On EDA05 May 2010 EDA360 unplugged with Cadence's Jaswinder Ahuja - Pradeep's Point04 May 2010 EDA360: My Modest Opinion - Gabe on EDA
 
April

29 Apr 2010 Cadence outlines vision with EDA360 - TechBites28 Apr 2010 Cadence Challenges Hardware Development Process - Printed Circuit Fab & Design27 Apr 2010 EDA Focus Shifts to Software - Chip Design Magazine27 Apr 2010 Cadence Tries to Incite Its Industry to Think Bigger - Wall Street Journal 27 Apr 2010 Cadence Tries to Incite Its Industry to Think Bigger - All Things Digital27 Apr 2010 Cadence Issues Blueprint to Battle 'Profitability Gap'; Counters Semiconductor Industry’s Greatest Threat - PC's Semiconductors Blog27 Apr 2010 Cadence Teams With Wind River, Rolls Verification Platform - EE Times27 Apr 2010 EDA360: The Way Forward for Electronic Design - EDA Design Line27 Apr 2010 Cadence Design Systems Shares EDA Vision for Semiconductor Industry - EDA Geek16 Apr 2010 Lord Kelvin on productivity and measurement — and how it relates to EDA - EDA DesignLine14 Apr 2010 They are here ... 3D ICs with through silicon vias (TSVs) - TechBites.com
 
March

22 Mar 2010 Cadence Acquires FPGA-Focused EDA Startup - EE Times 15 Mar 2010 Q5 Interview - Charlie Huang, Cadence Design Systems - Electronics Weekly01 Mar 2010 The rise of the CMO — but where M = Mobility - Yankee Group
 
February

22 Feb 2010 High-level synthesis, verification and language - Forte Design Systems19 Feb 2010 EDA chiefs hazard no guesses on 2010 market - EE Times16 Feb 2010 Is HLS finally converging on a standard language? - Forte Design Systems09 Feb 2010 EMA Expands OrCAD Product Family - PCB Design 00705 Feb 2010 Managing Complex SoC verification using plan based verification techniques - EDA DesignLine03 Feb 2010 Cadence introducing the new Encounter supporting 32nm and 28nm Designs - Electronic Journal02 Feb 2010 Si2 rolls open PDK effort - EE Times02 Feb 2010 Cadence Encounter 9.1 Addresses Industry Productivity Crisis - Gabe Moretti of GabeonEDA02 Feb 2010 Cadence adds design for manufacture to 32nm chips - Richard Wilson, Electronics Weekly01 Feb 2010 Latest Cadence Encounter Digital Implementation System is mind-boggling! - Clive Maxfield, Techbites01 Feb 2010 Cadence Encounter Digital Implementation System 9.1: avoiding incorrect by construction - Ron Wilson, Executive Editor of EDN01 Feb 2010 Cadence Encounter Digital Implementation System 9.1 addresses productivity crisis for complex SoC design - PC’s Semiconductor’s Blog, Pradeep Chakraborty01 Feb 2010 Cadence Encounter Digital Implementation System 9.1 Addresses Industry Productivity Crisis for Complex SoC Design - Low-Power Design01 Feb 2010 Cadence Encounter Digital Implementation System 9.1 - EDA Blog, Ken Cheung01 Feb 2010 Cadence Encounter Digital Implementation System 9.1: avoiding incorrect by construction - EDN01 Feb 2010 Cadence Encounter Digital Implementation System 9.1 addresses productivity crisis for complex SoC design - PC's Semiconductors Blog01 Feb 2010 Cadence adds design for manufacture to 32nm chips - Electronics Weekly
 
January

07 Jan 2010 A real solution for mixed signal SoC verification - EDA DesignLine