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December

18 Dec 2008 Viewpoint: Low-power design brings chip, software together - EE Times05 Dec 2008 Cadence offers open source OVM solution - EE Times03 Dec 2008 Cadence rolls multi-core design solution - EE Times03 Dec 2008 Cadence pulls together the pieces for 45, 32 nm design - EDN03 Dec 2008 RTL-to-GDSII Multicore Solution - Portable Design02 Dec 2008 Tomorrow's teardown - IET
 
November

07 Nov 2008 Reclaiming power margins - Power Management DesignLine Europe05 Nov 2008 Watch for the advent of Green EDA! - EE Times Europe04 Nov 2008 Early Dynamic Power Analysis and Pre-RTL Exploration Tool - Portable Design03 Nov 2008 A SystemC/TLM based methodology for IP development and FPGA prototyping - EDA Design Line
 
October

23 Oct 2008 Leakage and verification costs both continue to rise, says Cadence - Electronics Weekly23 Oct 2008 Empowered electronics - New Electronics22 Oct 2008 Turning the Power On at the System-Level for Power Analysis and Exploration - Chip Design Magazine09 Oct 2008 Chips Feel The Crunch - Electronics Market06 Oct 2008 The need to address power during manufacturing test - EDA DesignLine02 Oct 2008 Low power and a free lunch - Chip Design Magazine
 
September

30 Sep 2008 The OVM shines spotlight on automated metric-driven verification - Electronic Business23 Sep 2008 Si2 Announces Release of Common Power Format Version 1.1 - EDA Cafe 12 Sep 2008 The Promise & The Challenge - EDA Cafe12 Sep 2008 Green Power Moves Beyond the Buzz - Chip Design Magazine10 Sep 2008 CDNLive Panel on Green Power and IT - Chip Design Magazine09 Sep 2008 CDNLive! Silicon Valley 2008—Future Visions and Today’s Newest Design Technologies - Cadence Design Systems09 Sep 2008 Cadence Launches Hosted Design Service - New Electronics09 Sep 2008 Execs want green data centers - CNET03 Sep 2008 Special technology report - Low power design - SCD Source
 
August

21 Aug 2008 Capturing and communicating power-efficient design knowledge - Power Management DesignLine Europe 20 Aug 2008 The Shaughnessy Report: Hemant Shah of Cadence on Constraint-Driven HDI Design - PCB00719 Aug 2008 ESL: The state of the industry and what's next? - Electronic Business12 Aug 2008 Ted Vucurevich's Executive Perspective at DAC 2008 - International Engineering Consortium12 Aug 2008 Adam Traidman's Executive Perspective at DAC 2008 - International Engineering Consortium06 Aug 2008 User Advisory Group Established to Guide Evolution of the Open Verification Methodology - Yahoo Finance
 
July

18 Jul 2008 Transaction-Based Acceleration: A Second Generation Introduces Even More Power - Chip Design Magazine14 Jul 2008 Cadence C-to-Silicon synthesis may mark next round in ESL tools - EDN14 Jul 2008 Cadence claims 'next generation' high-level synthesis - SCD Source08 Jul 2008 ESL Handoff: Closer Than You Think - EDA DesignLine08 Jul 2008 A Holistic Approach to Analogue Spice Simulation Speeds IC Verification - New Electronics
 
June

16 Jun 2008 Russia moving on fabless development path, says Cadence - EE Times Europe16 Jun 2008 EDA healthy and growing in India - CIOL12 Jun 2008 Mobile growth: 'Exponential curve' or Dead Man's Curve? - EE Times12 Jun 2008 Prestigious Panel Recognizes Important Industry Innovations at SEMICON West - Nanowerk12 Jun 2008 2007 International Test Conference papers - IEEE10 Jun 2008 Cadence, Synopsys Team with ARM for 45-nm Low Power Common Platform Flow - Electronic News10 Jun 2008 Reference Design Targets UMC 65nm Process - Electronics Talk10 Jun 2008 Verification IP Products Suit OVM Users - Electronics Talk10 Jun 2008 Cadence, Synopsys team with ARM for 45-nm low power Common Platform flow - EDN10 Jun 2008 Reference design targets UMC 65nm - Electronics Talk06 Jun 2008 European User Conference Addresses Design Automation Challenges - Components in Electronics
 
May

20 May 2008 May Institute gets $1M from California company - Boston Business Journal18 May 2008 49ers Take Part in Stars and Strikes - 49ers.com15 May 2008 Unified EDA Flow for Analog Designs and PCB Implementation - SMT06 May 2008 How floorplanning guides synthesis and physical design - SCD Source06 May 2008 DRC signoff doesn't cut it for next-gen nodes - EE Times01 May 2008 Toward a standard deep sub-micron analog design flow: Cadence enhances the Virtuoso Platform - EDN
 
April

29 Apr 2008 Cadence offers new custom IC design capabilities - SCD Source29 Apr 2008 Cadence Debuts RTL to GDSII Reference Flows for ARM Cortex-A9 - EDA Geek28 Apr 2008 New standards effort targets verification IP interoperability - SCD Source28 Apr 2008 Q&A: Cadence's Vucurevich On Processing Power's Continued Importance - Gamasutra28 Apr 2008 Accommodating Change - IC Journal22 Apr 2008 What floorplan information is needed for synthesis - EDA DesignLine22 Apr 2008 Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems - Chip Design Magazine17 Apr 2008 Cadence Announces Reentry Into Upstream Design in Japan - Tech-On!17 Apr 2008 Validating false path timing exceptions - SCD Source17 Apr 2008 Virage Logic adds 65-nm Common Power Format low-power standard cell libraries to portfolio - EDN15 Apr 2008 It's time to shift the low power debate - SCD Source12 Apr 2008 Multi-language Functional Verification Coverage for Multi-site Projects - EDA DesignLine04 Apr 2008 Viewpoint: Verification flow should be front and center - EE Times01 Apr 2008 Open Verification Methodology: Why Now? - EDA DesignLine01 Apr 2008 'Openness' fulfills SystemVerilog promise - EE Times Asia
 
March

31 Mar 2008 On-Chip Thermal Analysis Is Becoming Mandatory - Chip Design Magazine31 Mar 2008 Tool Automates Engineering-Change-Order Generation - Electronic Design25 Mar 2008 Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems - Chip Design Magazine21 Mar 2008 Power Forward group launches low-power design methodology guide - EDN20 Mar 2008 PFI releases low-power design user guide - CIOL19 Mar 2008 The Perils of 45nm: A Report on the Move - IET TV18 Mar 2008 How to specify and verify power-cycled SoCs for checking and coverage - Electronic Business10 Mar 2008 Practical Case Study In Low-Power Design Methodology - EPN Online06 Mar 2008 Is it really a black art or just a red herring? - DAC e-Zine06 Mar 2008 Addressing manufacturing variation at advanced nodes with silicon-contour-based DFM - Solid State Technologies05 Mar 2008 If you can't measure progress against your plan, you have no plan! - Chip Design Magazine05 Mar 2008 Addressing manufacturing variation at advanced nodes with silicon-contour-based DFM - Solid State Technology
 
February

27 Feb 2008 Power mode technologies verify today's SoCs - EE Times26 Feb 2008 Improving design turn around time on a complex SoC by leveraging a reusable low power specification - Design & Reuse25 Feb 2008 Formal verification expands its use model - SCD Source22 Feb 2008 Pizarro: Bowling benefit to aid autistic children - San Jose Mercury News21 Feb 2008 The Brewing Standards War - Verification Methodology - Cool Verification18 Feb 2008 Multi-language Functional Verification Coverage for Multi-site Projects - EDA DesignLine13 Feb 2008 Where's the ROI in DFM? - EDN11 Feb 2008 SPIE and the IC design world: a wall starts coming down - EDN06 Feb 2008 Open Verification Methodology offers interoperability - SCD Source05 Feb 2008 IEC Today Announces Winners of Highly-Coveted DesignVision Awards at DesignCon 2008 - International Engineering Consortium
 
January

29 Jan 2008 A Methodology to Speed DFT Signoff - Evaluation Engineering23 Jan 2008 Cadence Encounter RTL Compiler wins synthesis poll - EE Times21 Jan 2008 Automated Formal Verification of OCP based IP Cores - EDA DesignLine16 Jan 2008 Coverage-driven verification for mixed-signal systems - SCD Source14 Jan 2008 Commentary: 'Open' is (not) just a four-letter word - EE Times09 Jan 2008 "Let the mayhem begin!": Open Verification Methodology available for free download - EDN09 Jan 2008 Cadence, Mentor roll verification tool - EE Times09 Jan 2008 Open Verification Methodology ready for download from Cadence, Mentor - EDN04 Jan 2008 Physical predictability for carbon-neutral timing closure - EE Times02 Jan 2008 Ten 2008 Trends in System and Chip Design - SCD Source01 Jan 2008 Executive Outlook: Driving Productivity, CoO in 2008 - Semiconductor International