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December

31 Dec 2007 Verification Platform for Complex Designs - EDA DesignLine18 Dec 2007 Addressing low-power issues in chip design - CIOL17 Dec 2007 Everybody loves Cadence; can EDA leader sustain the romance? - EE Times06 Dec 2007 Electronic Design Winners - Electronic Design05 Dec 2007 ARC readies energy saving cores - EE Times04 Dec 2007 Accelerating Simulation While Preserving a Familiar Verification Environment - Chip Design Magazine03 Dec 2007 Cadence makes logic verification OVM-savvy - EE Times03 Dec 2007 Cadence upgrades Enterprise verification suite - SCD Source03 Dec 2007 Cadence upgrades enterprise verification offering - EE ProductCenter
 
November

28 Nov 2007 The Madness of Randy Stude and the triumph of the PC gaming platform - San Jose Mercury News27 Nov 2007 Cadence opens design office in Zelenograd - EE Times19 Nov 2007 I Know What You Didn't Verify Last Summer! - EDA DesignLine09 Nov 2007 Zero-Degrees of Freedom at 45nm - Chip Design Magazine08 Nov 2007 Creating a chip is as complex as building an aircraft - Financial Express05 Nov 2007 Design with Verification: Not an Oxymoron - EDA DesignLine
 
October

29 Oct 2007 Reducing Risk in Wireless Design - Wireless Week29 Oct 2007 Accelerating Functional Verification - EDA DesignLine25 Oct 2007 Panelists: 45 nm requires collaborative 'ecosystem' - SCD Source24 Oct 2007 CPF-Based, Low-Power Digital Reference Flow - Chip Design Magazine22 Oct 2007 Ensuring Power Designing Works at 65nm - EDA DesignLine18 Oct 2007 Ensuring Reliable and Optimal Analog PCB Designs With Advanced Analysis for Spice Simulation - Circuitree17 Oct 2007 Column: Redefining research and development for the 21st century - Electronic Business16 Oct 2007 Truly Open Verification Methodology - Chip Design Magazine16 Oct 2007 Cadence, Mentor unify SystemVerilog method - EE Times Asia15 Oct 2007 IBM, AMD, Nvidia, Intel Talk The Future Of Processors - Gamasutra11 Oct 2007 Semi industry faces manufacturability, complexity and scale issues: Cadence CEO - EE Times11 Oct 2007 Low Power Designs from a CPF Perspective - EDA DesignLine11 Oct 2007 Nvidia, ATI/AMD look beyond GPUs toward unified gaming engines - EDN10 Oct 2007 Low power flows still need work, speakers say - SCD Source08 Oct 2007 Signoff for Manufacturability - EDA DesignLine
 
September

26 Sep 2007 Bringing Physical Predictability to Logic Design - Electronic Design25 Sep 2007 Dr. Robert Brayton to be honored as 14th Kaufman Award Winner - EDN24 Sep 2007 Cadence DFM - WYDIWYG; Interview with Mike McAweeney - EDA Cafe24 Sep 2007 Cadence cuts ribbon on Berkeley applied research lab, gives $10K to high school - Electronic News17 Sep 2007 Measure power efficiently, effectively—and early - EE Times11 Sep 2007 Process Intelligent Modeling and Statistical STA improve DFM - EDA DesignLine11 Sep 2007 Cadence Provides "WYDIWYG" Capability, Collaborates with Stratosphere Solutions - EDA DesignLine11 Sep 2007 Cadence fills out DFM flow in time for 45-nm design - EDN10 Sep 2007 Cadence fills out DFM flow in time for 45-nm design - EDN07 Sep 2007 Open Verification Methodology Relieves Inefficiencies - Electronic Design06 Sep 2007 Cadence adds debug tool for verification - Electronics Weekly04 Sep 2007 The great American ideas factory - BBC News04 Sep 2007 Building a Transaction-Based Acceleration Regression Environment - Chip Design Magazine
 
August

30 Aug 2007 RF-A/MS IC Functional Verification: Requirements and Methodology, Microwave Journal - Microwave Journal27 Aug 2007 Verifying your low-power designs - Power Management DesignLine27 Aug 2007 Hot Chips, Cool Books, Brainiacs & Workaholics Abound, EDA Cafe - EDA Cafe27 Aug 2007 SoC technology underscores need for verification - EE Times27 Aug 2007 Hot Chips, Cool Books, Brainiacs & Workaholics Abound - EDA Cafe27 Aug 2007 Verifying your low-power designs - Power Management DesignLine17 Aug 2007 Signoff for manufacturability - an absolute necessity at 45-nm - EDN16 Aug 2007 Cadence and Mentor create free, open-source SystemVerilog methodology - EDN16 Aug 2007 EDA picking up, 45nm design challenges, Achilles and standards, and Brian Fuller's new gig - EDN16 Aug 2007 EDA DesignLine Engineering Blog - EDA DesignLine08 Aug 2007 Using HW emulators to get HW/SW right the first time on the Sun UltraSPARC T1 processor - Programmable Logic DesignLine06 Aug 2007 Making Verification Methodology and Tool Decisions - EDA Design Line02 Aug 2007 Where have all the margins gone? - EDN02 Aug 2007 Winbond adopts Cadence emulator to ease verification - EE Times Asia
 
July

31 Jul 2007 Software Options Captures RF Design Intent - Microwaves & RF30 Jul 2007 Challenges at the 45-nm node are great - EE Times19 Jul 2007 Analog/Full-Custom Flows Move Toward Interoperability - Electronic Design13 Jul 2007 Getting Back to Basics with Planning, Metrics, and Management - EDA DesignLine13 Jul 2007 Rescuing Moore's Law with "verification computers" - EDN10 Jul 2007 Editor's Choice: Cadence's Allegro System Interconnect Design Platform - RF Globalnet10 Jul 2007 The software coverage plan - IET09 Jul 2007 Cadence Logic Design Team Solution Answers Logical-Physical Closure Conundrum - SOC Central09 Jul 2007 Floorplanning, RTL synthesis link up for chip-level interconnect - EE Times05 Jul 2007 Commentary: Imagination turns to reality in verification - EE Times
 
June

28 Jun 2007 Low-power Methodology Kit - Wireless Design & Development26 Jun 2007 Commentary: SystemVerilog enables design with verification - EE Times20 Jun 2007 Designing "with" instead of "for" - EDN18 Jun 2007 Extraction Tool Makes Grade On TSMC's 45-nm Process - Electronic Design18 Jun 2007 Design Constraint Verification and Validation: A New Paradigm - EDA DesignLine13 Jun 2007 Verification of a single-chip Analog TV and Digital TV ASIC - Digital TV DesignLine13 Jun 2007 Introducing a New Approach to Wireless IC Design - Wireless Design & Development12 Jun 2007 Meeting Aggressive Project Schedules with Fixed Design and Verification Resources - Chip Design Magazine12 Jun 2007 Instructional Software Kit Simplifies RF IC Design - Microwaves & RF07 Jun 2007 Productivity Gains Eliminate Verification Bottlenecks - Electronic Design05 Jun 2007 DAC special: Video interview with Cadence's Ted Vucurevich - EE Times04 Jun 2007 Common Platform debuts DFM support at 45-nm - EDN04 Jun 2007 It's Time To Lift The Burden From Logic Designers - Electronic Design
 
May

29 May 2007 Cadence attacks assertion-based verification bottlenecks - EE Times22 May 2007 RF SiP Methodology Kit - Wireless Design & Development22 May 2007 RF SiP Methodology Kit - Wireless Design & Development21 May 2007 Software extensions to functional tools handle co-verification in SoCs - EE Times21 May 2007 Coverage-Driven Methodology for SoC Development Critical for Success - Chip Design16 May 2007 Delivering advanced SystemVerilog verification capabilities to design teams - EDN16 May 2007 Kit cuts the cost of low-power IC design - Electronics Talk15 May 2007 Analog Mixed Signal Methodology Kit - Wireless Design & Development15 May 2007 Chipmakers take a global perspective - SF Chronicle15 May 2007 Cadence offers low-power-methodology kit - EDN14 May 2007 Cadence 'kit' eases low-power IC design - EE Times14 May 2007 Pizarro: Taking the initiative to make a difference - San Jose Mercury News14 May 2007 Methodology Kit Speeds Adoption of Low-Power Designs - Chip Design14 May 2007 Cadence Speeds Adoption of Wireless and Consumer Low-Power Designs with Low-Power Methodology Kit - Design and Re-use
 
April

30 Apr 2007 Unified Verification of SoC Hardware and Embedded Software - Chip Design Magazine24 Apr 2007 Rigorous Automated Verification Yields High Quality Silicon - EDA DesignLine24 Apr 2007 Award recognises advancement of women in EDA - Electronics Talk23 Apr 2007 Cadence debuts 65-nm reference flow targeting Common Platform - Electronic News12 Apr 2007 Efficient Computing and Advanced Visualization Accelerates Electronic Design - EDA DesignLine06 Apr 2007 Women of Distinction Awards Pay Tribute to Some of Silicon Valley's Most Powerful and Inspiring Women - Forbes.com06 Apr 2007 Winner: Jan Willis - Silicon Valley/San Jose Business Journal06 Apr 2007 Lower power becomes bigger issue - EDN06 Apr 2007 Lower Power becomes bigger issue - EDN
 
March

29 Mar 2007 Pragmatic Adoption of Formal Analysis - EDA DesignLine29 Mar 2007 Use SystemVerilog for coverage metrics - EDN19 Mar 2007 A System-Level Verification Flow for EDA - EE Times16 Mar 2007 Manage verification with success - EETimes Asia15 Mar 2007 Cadence platform enables Taiwan's first 65nm chip design - EETimes Asia08 Mar 2007 Solving PCB Design Interconnect Challenges - Printed Circuit Design & Manufacturing Magazine07 Mar 2007 Mike Fister talks about Cadence's role in the electronics industry - Wall Street Reporter05 Mar 2007 Faster Verification is the Goal at ST - EE Times05 Mar 2007 A Simple New Approach to Hardware Software Co-Verification - Embedded05 Mar 2007 Common Power Format 1.0 Released by Si2's Low Power Coalition - SI204 Mar 2007 How to achieve predictable front-end power closure - Power Management DesignLine01 Mar 2007 Integrating Power Awareness into IC Design - EDA DesignLine01 Mar 2007 Focus On Power-Efficient Design To Help Stop Global Warming - Electronic Design01 Mar 2007 Freescale Shrinks EDA Tool Flows - EE Times
 
February

22 Feb 2007 An Enterprise-wide Approach Accelerates Next-Generation System-level Development - EDA DesignLine22 Feb 2007 DVCon Keynote: Verification Takes a Broader View - EE Times22 Feb 2007 Methodology and Flow Challenges in Multi-die Package Design - Advanced Packaging19 Feb 2007 Plan your verification with SystemVerilog - EE Times16 Feb 2007 Pizarro: Engineering center 'just the beginning - San Jose Mercury News15 Feb 2007 Common Power Format Comes To Fruition In Tool Suite - Electronic Design13 Feb 2007 Commentary: EDA vendors must deliver a complete low-power solution - EDN08 Feb 2007 Cadence to break ground on new San Jose headquarters - Silicon Valley Business Journal08 Feb 2007 Is Your System-Level Project Benefiting from Collaboration or headed to Chaos? - Chip Design Magazine06 Feb 2007 Guest commentary: 65-nm IC designs need DWT as well as DFM - Test & Measurement World02 Feb 2007 Error Checking and Functional Coverage with SystemVerilog Assertions - SOC Central02 Feb 2007 Does 65-nm Design Require DFM Tools? - EDN01 Feb 2007 'Design with Test' for Low-Power Devices - Electronic Engineering Times-Asia01 Feb 2007 Metric-driven Methodology Speeds the Verification of a Complex Network Processor - Chip Design01 Feb 2007 Testing Challenges of a Multicore Microprocessor - Evaluation Engineering01 Feb 2007 Panelists: Front-end design needs overhaul - EE Times01 Feb 2007 One on one with Ted Vucurevich - EDN01 Feb 2007 Freescale opts for AMS kit from Cadence - Wireless Net Design Line
 
January

31 Jan 2007 Model-based DFM is the Way to Go, Panelists Agree - EDN30 Jan 2007 Router Wins DesignCon Award - EE Times30 Jan 2007 Notes Are Not Enough - IET30 Jan 2007 Software Preserves Low-Power Design Intent - Electronics Talk29 Jan 2007 Cadence Rolls Low-Power Design Flow - EE Times29 Jan 2007 What Cadence's CPF Looks Like - EE Times29 Jan 2007 How to Architect,Design,Implement and Verify Low-Power Digitial Integrated Circuits - EDA Design Line29 Jan 2007 IC-Tool Flow Supports New Power Standard - EDN26 Jan 2007 Router improves design and manufacturability - ElectronicsTalk25 Jan 2007 ST tapes out 65nm mixed-signal design with Cadence router - EDN23 Jan 2007 Facing the Challenge - New Electronics19 Jan 2007 The Future of the Semiconductor Design - EDN17 Jan 2007 Parser supports Cadence IC power standard - EE Times17 Jan 2007 Cadence releases Common Power Format source code - EDN15 Jan 2007 Planning for Assertion-Based Verification - EE Times12 Jan 2007 Si2 approves low-power spec, seeks 'convergence' - EE Times11 Jan 2007 IEC Announces 2007 DesignVision Finalists Recognizing Best Tools and Products in Semiconductor Industry - Business Wire08 Jan 2007 SystemVerilog Adoption Up, Cadence Survey Says - EE Times05 Jan 2007 Remembering Richard Newton: Technology Visionary - Cadence03 Jan 2007 Realizing System-level Design and Verification Success: A Holistic Approach - Cadence Design Systems, Inc.03 Jan 2007 Making It Easier to Get Started with the Plan-to-Closure Methodology Version 6.0: Addressing Verification Productivity, Predictability, and Quality - Cadence Design Systems, Inc.03 Jan 2007 Yes or no? An Executive Guide to Making Verification Methodology and Tool Decisions - Cadence Design Systems, Inc.03 Jan 2007 Beyond the Compliance Checklist - Cadence Design Systems, Inc.03 Jan 2007 ARM-based Testing: Simple Steps to Ensure Success - Cadence Design Systems, Inc.03 Jan 2007 si_util: A Utility Library Package for the e Language - Cadence Design Systems, Inc.