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19 Dec 2006 Cadence claims RTL synthesis boost - EE Times18 Dec 2006 Newer Hardware Acceleration and Verification Systems Bringing Something New to the Table - Electronic Design18 Dec 2006 Practical Applications of Statistical Static Timing Analysis - EDA DesignLine18 Dec 2006 Beating the Debug Delivery Rush using Packaged Metrics - EDA Cafe15 Dec 2006 Suite Automates Hardware, Software, And System-Level Verification - Electronic Design13 Dec 2006 Wipro Selects Cadence As Primary Tool Provider - EE Times11 Dec 2006 Holistic Capabilities Imperative for Design, Says Cadence Exec - EE Times India06 Dec 2006 Cadence CEO Talks About Semicon Design - EE Times India05 Dec 2006 ESL Market Adds an Enterprise Player - EDN04 Dec 2006 Enterprise System Level Verification Brings New Life to ESL - EDN04 Dec 2006 Verification Tools Bring ESL to Enterprise - EE Times04 Dec 2006 "Enterprise" System Level (ESL) Verification" PART II - EDA Design Line04 Dec 2006 Cadence Rolls Out Enterprise ESL Verification - Electronic News

29 Nov 2006 Cadence Upgrades Virtuoso Custom Design Platform - EETimes India22 Nov 2006 Mixed-Signal Simulation For Automotive Sensor Design With Design Checking And Self-Assessment - Planet Analog22 Nov 2006 Design RFICs With Greater Speed, Accuracy - Embedded.com20 Nov 2006 We Need "Enterprise" System-Level Solutions - EDA DesignLine09 Nov 2006 Designing Consumer Electronics: Feeling the Squeeze - EDN07 Nov 2006 10 Crucial Elements of Building an Innovative Company - Electronic Business06 Nov 2006 A Hardware-Assisted Verification System For The Masses Arrives On Desktops - Electronic Design05 Nov 2006 Pushing Power Forward with a Common Power Format - EE Times03 Nov 2006 Commentary: Why It's Time to Redefine ESL - EE Times01 Nov 2006 Dynamic Summits from Cadence and Microsoft - Advanced Packaging01 Nov 2006 Cadence Moves to Avert Power Standards War; Aligns with Si2 - EE Times01 Nov 2006 Mike Fister, President and Chief Executive Officer, Cadence Design Systems, Inc., Presides Over the Market Open - NASDAQ

30 Oct 2006 Time Not Ripe for 450-mm Wafers - EDN30 Oct 2006 MathWorks Links Tool to Cadence - EE Times25 Oct 2006 New Tools Integrate Design and Verification - EDN24 Oct 2006 Cadence Turns to "Schedule Predictability Crisis" in RTL Design - Electronic Design23 Oct 2006 Let Metrics Help with Verification - EE Times23 Oct 2006 Cadence Addresses Logic-design Predictability Crisis - Test & Measurement World23 Oct 2006 Cadence Addresses Predictability Crisis - Electronic News23 Oct 2006 Front-end Design Methodologies Must Address the Challenges of Today's Process Technologies and Economic Realities - EDA DesignLine23 Oct 2006 Logic Design Gets Scheduling Boost - EE Times23 Oct 2006 The Predictability Crisis: Predictable? - Electronic News23 Oct 2006 Far Out Future for Mobile Media - BBC News16 Oct 2006 Chipmakers Turning to Software Support - Moneycontrol.com12 Oct 2006 Emerging Markets a Big Opportunity, Fister says - EE Times11 Oct 2006 Leveraging the cutting edge for performance, power, function - Electronic News11 Oct 2006 Cadence CTO calls for power savings in chip design - eWEEK.com09 Oct 2006 A holistic approach to system-level design and verification success - EDA DesignLine09 Oct 2006 Emulation gets the nod vs. FPGA prototyping - Chip Design Magazine01 Oct 2006 Qualcomm, Cadence implement DFT for CDMA devices - Test & Measurement World

28 Sep 2006 Circulating currents: The warnings are out - EDN27 Sep 2006 Cadence ranks near top on list of IT Innovators in "InformationWeek 500" - Information Week26 Sep 2006 PODCAST: EDA melds art and science - Electronic Business18 Sep 2006 What's Your Verification Game "Plan"? - Chip Design Magazine14 Sep 2006 Cadence upgrades EDA platform - The Hindu Business Line13 Sep 2006 Virtuoso becomes a 'native' OpenAccess application - EE Times Asia12 Sep 2006 System eyes hardware-assistance hurdles - EE Times12 Sep 2006 Cadence presents roadmap, tips 'Torino' - EE Times12 Sep 2006 Cadence eyes India advantage for chip development - Business Standard12 Sep 2006 Cadence Expands Reach for Hardware-Assisted Verification - Electronic News12 Sep 2006 System-Level Verification Takes More Than Just Speed - Electronic Design11 Sep 2006 Flexible Constraint-Management Drives Next-Generation Mixed-Signal Design - EE Times11 Sep 2006 Analog/mixed-signal IC design evolves to meet new challenges - Planet Analog11 Sep 2006 Cadence retunes Virtuoso for OpenAccess - Electronics Weekly11 Sep 2006 Cadence Overhauls Custom IC Design Platform - EDN11 Sep 2006 Cadence Retunes Virtuoso - EE Times08 Sep 2006 Routing technology came from within Cadence, execs say - EE Times06 Sep 2006 Accellera considers power format standards effort - EE Times05 Sep 2006 How RF SiP technology is moving into the wireless design mainstream: Part 3: SiP design flow implementation - Wireless Net DesignLine05 Sep 2006 Cadence moves to broaden power initiative - EE Times05 Sep 2006 Cadence Adds Timing Signoff to Encounter Platform - EDN05 Sep 2006 Cadence rolls 'signoff quality' timing analysis - EE Times01 Sep 2006 How to best marry time-domain system-level verification with frequency-domain RF circuit simulations - RF Design01 Sep 2006 An overview of on-chip compression architectures - EDN01 Sep 2006 Reusable Verification IP Fits Into Overall Automation Planning - Electronic Design

31 Aug 2006 Best Employers: The sixth comprehensive annual survey of Indian tech companies - DataQuest India28 Aug 2006 How RF SiP technology is moving into the wireless design mainstream: Part 2: The ideal RF SiP Flow - Wireless Net Design Line28 Aug 2006 Enhancing Flows When Moving Manufacturing into IC Design - Solid State Technology24 Aug 2006 Assertive Methodology Key to Scalable Formal Analysis Deployment - Electronic News22 Aug 2006 How RF SiP Technology is Moving into the Wireless Design Mainstream - Wireless Net DesignLine21 Aug 2006 Virtual Prototyping Speeds Mixed-Signal IC Design - EE Times14 Aug 2006 Full-chip Verification for Analog/Mixed-Signal ICs - EE Times14 Aug 2006 Cadence Targets IP Verification Bottleneck - EE Times08 Aug 2006 Transitioning to Manufacturing-aware Design - Electronic Design07 Aug 2006 Capturing and Applying Design Intent - EDA DesignLine07 Aug 2006 Cadence Offers Reusable Verification IP - Electronic News07 Aug 2006 Cadence Verification IP Claims Broad Language Support - EE Times07 Aug 2006 It's Time to Abstract Higher-Levels of Performance from Your Verification Process - Chip Design Magazine07 Aug 2006 Verification IP Takes a Broader Role - EE Times

31 Jul 2006 Cadence Addresses DFT, DFM, and Power - Test & Measurement World27 Jul 2006 Audiocast: One on One with Mike Fister - Electronic News25 Jul 2006 Interview with Cadence Research Scientist and DAC Chair Ellen Sentovich - EE Times24 Jul 2006 Designing Without a Net: Restricted Design Rules Challenge DFM's Role - EE Times24 Jul 2006 Mixed-Signal Design Challenges - Portable Design24 Jul 2006 Questions with Cadence's Jim Miller - Electronic News24 Jul 2006 Cadence, Mentor Spar in High-Speed Realm - EE Times24 Jul 2006 Toward Surgical Approach to Design - EE Times20 Jul 2006 Space-Based, Full-Chip Router Takes On Mixed-Signal And Custom-Digital Designs - Electronic Design18 Jul 2006 It's Time to Abstract Higher-Levels of Performance from Your Verification Process - Chip Design Magazine18 Jul 2006 India Design Firms as Product Innovators - Electronic Business17 Jul 2006 Cadence CTO Ponders EDA's Role - EE Times17 Jul 2006 Pulse-Latch Approach Reduces Dynamic Power - EE Times17 Jul 2006 Cadence CTO Ponders EDA's Role - EE Times10 Jul 2006 Getting the Most Out of RTL Logic Synthesis - EE Times06 Jul 2006 Save Those Watts With a Power-Aware Design Flow for SoCs - Electronic Design06 Jul 2006 Is Chip Design Different After 90nm? - EDN05 Jul 2006 Verification Languages: 3 points to ponder beyond "which one?" - EDA Cafe01 Jul 2006 Litho Simulation Enables the Leading Edge - Semiconductor International01 Jul 2006 Optimizing the Interface Between Design and Manufacturing - Semiconductor International01 Jul 2006 Life after DFM - Electronic Business

26 Jun 2006 Cadence intros ARM verification kit - EE Times26 Jun 2006 Cadence mainstreams RF SiP design - Wireless Net DesignLine26 Jun 2006 System-in-package tools roll - EE Times26 Jun 2006 Constraint-driven physical design speeds IC convergence - EE Times26 Jun 2006 Cadence tackles SiP, verification issues - EE Times Germany26 Jun 2006 Cadence Leverages Shape-based Routing - Electronic News26 Jun 2006 Cadence delivers space-based, full-chip router - Test & Measurement World26 Jun 2006 Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort - SoC Central26 Jun 2006 Routing Tool Retains Data for Incremental Improvement - Electronic Weekly22 Jun 2006 Initiative Looks To Establish Low-Power Design Infrastructure - Electronic Design19 Jun 2006 Cadence Cozies Up to Hong Kong R&D Institute - Electronic News15 Jun 2006 Inclusive Design and Verification Methodologies will Drive Next Generation SoCs - Electronic News15 Jun 2006 DFM Becomes More Than Hype - Semiconductor International14 Jun 2006 Innovation vs. Standardization - Electronic News13 Jun 2006 Mother Knows Best - New Electronics12 Jun 2006 PDK Functionality Tackles Length of Diffusion Effects - EE Times12 Jun 2006 Will Analog-RF Designs Ever Truly Fit in the SoC World? - Chip Design12 Jun 2006 System-level Verification Tool Rolls - EE Times06 Jun 2006 Lithography Becomes Big Bottleneck - Electronic News05 Jun 2006 The Need for Verification Management - EE Times05 Jun 2006 Secrets and Dice: Process Challenges - Electronic System & Software05 Jun 2006 Facilitating System-in-Package (SiP) Design - EE Times02 Jun 2006 Bowlers, 49ers Team Up to Raise Funds for Stars and Strikes - Valley/San Jose Business Journal01 Jun 2006 IEEE Standardizes 'e' Language - EE Times Asia01 Jun 2006 Surfing Makimoto's Wave - Electronic Business01 Jun 2006 Test's Role on the Path to Zero-defect Devices - Test & Measurement World

25 May 2006 TSMC, UMC Ready for 65-nm X Architecture Designs - EE Times25 May 2006 TSMS,UMC Ready for 65-nm XArchitecture Designs - EE Times22 May 2006 Initiative Seeks Common IC Power Format - EE Times22 May 2006 Cadence Led Initiative Seeks Low Power Standard - ElectronicNews22 May 2006 Standard Format to Automate Low Power IC Design - ElectronicsWeekly19 May 2006 Sounding a New Cadence - Electronic News15 May 2006 Optimization Techniques Rein in IC Power Flow - EE Times15 May 2006 TSMC Lifts Lid on Foundry Process Data - EE Times11 May 2006 The Future of EDA? - Wireless Net DesignLine11 May 2006 Designers Cast a Skeptical Eye on Mixed-signal SOCs - EDN.com10 May 2006 New Supercomputing Center to Advance the Science of Nanotechnology - Rensselaer Polytechnic Institute08 May 2006 India's KPIT Picks Cadence Analog/Mixed-signal Methodology - EE Times08 May 2006 Assertion-based Verification Delivers Rewards - EE Times08 May 2006 Scheme eyes test tool mix and match - EE Times08 May 2006 The New Frontier—How Verification IP Will Define Processes and Automation That Will Increase Project-level Predictability and Productivity - Electronic News01 May 2006 Protect Your IP - Electronic Business

27 Apr 2006 Keys to Simulation Acceleration and Emulation Success - EDN27 Apr 2006 Cadence Segments PCB Product Line - EE Times26 Apr 2006 Cadence, PDF in DFM Collaboration - EE Times25 Apr 2006 Encrypting Process Information for Litho-aware OPC Models - Solid State Technology24 Apr 2006 A Balanced Approach to Chip Optimization - EE Times24 Apr 2006 Novices Get the IC Picture - EE Times19 Apr 2006 Agere, Cadence Partner to Speed TTM of Advanced Designs - Electronic News17 Apr 2006 Hope Seen for Taming IC Process Variability at Next Design Node - EE Times17 Apr 2006 Soothing Balm for Bleeding Edge Litho - EE Times13 Apr 2006 Cadence, SMIC Offer Analog/Mixed-Signal Reference Flow - EE Times11 Apr 2006 The India Advantage - EDN Asia11 Apr 2006 Cadence CTO: CAD "Foundations" Must Change - EE Times10 Apr 2006 Adapting Signal Integrity to Nanometer IC Design - EE Times10 Apr 2006 Verification: IEEE Standardizes 'e' Language - EE Times10 Apr 2006 Worry-free IP: A Once Blurry Vision Coming Into Focus - Electronic Design03 Apr 2006 PCI Express Verification Underscores Need to Plan - Electronic Engineering Times01 Apr 2006 Chips and Biryani - Forbes.com01 Apr 2006 The Critical Role of Design in Nanometer Process Yield - Nanochip Technology Journal

31 Mar 2006 IEEE Standardizes 'e' Verification Language - EE Times28 Mar 2006 EDA Must Free Designers To Focus On Differentiation - Electronic Design27 Mar 2006 Risk on the Rise - Electronic News24 Mar 2006 Fueling Innovation with Vertical Re-aggregation - Solid State Technology13 Mar 2006 Design For Manufacturing Shakes Up EDA Status Quo - Electronic Design09 Mar 2006 Lithography Awareness Reaches Front-End Design Tools - Electronic Design09 Mar 2006 Cadence distributor to target select custom IC customers - EE Times07 Mar 2006 Cadence Targets Verification Bottleneck Through "Knowledge System" - EE Times07 Mar 2006 Si2 Releases Current-source Model Standard for Design Libraries - EE Times03 Mar 2006 Demystify Power Gating and Stop Leakage Cold - Power Management Design Line03 Mar 2006 IP in China: Opportunity and Risk - Electronic News02 Mar 2006 Full-Chip Optimization Tool Boosts ICs' Yield And Performance - EE Design02 Mar 2006 Design Tools Challenged at 45nm - EE Times02 Mar 2006 PodTech News Podcast: Ajay Malhotra of Cadence Design Systems - PODTECH.net02 Mar 2006 CEO Viewpoint: Consumers Drive R&D Focus on Size, Power - Electronics Weekly

28 Feb 2006 Designs on a Common Platform - Semiconductor Fabtech28 Feb 2006 Silicon Design Chain - Second Power Management Methodology - IQ Online22 Feb 2006 Is Schematic-based Design Obsolete? - Printed Circuit Design & Manufacture20 Feb 2006 Analysis: Fresh Fixes for Industry's RET Addiction - EE Times17 Feb 2006 Cadence's Virtuoso RET Suite puts 'design back into DFM' - EE Times Asia17 Feb 2006 The IC Package—Missing Link Between Nanometer Silicon and Multi-gigabit PCB Systems - Advanced Packaging15 Feb 2006 Verification Tools Help PHS Transceiver Take Silicon Form - Microwaves & RF14 Feb 2006 Suite Makes IC Designs More Manufacturable - ElectronicsTalk13 Feb 2006 Cadence Spins "Secure" DFM Model, Makes Custom Layout Litho Savvy - EDN13 Feb 2006 Lithography-aware Design Enables "Extreme" RET - EE Times13 Feb 2006 Cadence Litho-aware DFM Tool Aims to Improve Yield - Electronic News12 Feb 2006 Cadence Rolls RET Into Flow - EE Times08 Feb 2006 Innovators of Electronic Design Honored - Electronic News08 Feb 2006 DFM Has Potential to Build Partnerships, But Will It? - Electronic News02 Feb 2006 Co-design: EDA Vendors Are Helping IC and Package Designers More Effectively Work Together - EDN01 Feb 2006 Improving Design and Manufacturing Through Design-enabled Lithography - Semiconductor International

30 Jan 2006 Cadence's 'Catena' rolls layout optimizer - EE Times30 Jan 2006 In-house startup delivers DFM tool - EE Times26 Jan 2006 Physical Verification in the Age of One Billion Transistors, One Thousand Design Rules, and Million Dollar Mask Sets - Electronic Design19 Jan 2006 Methodology Kit Demystifies Wireless Design - Electronic Design19 Jan 2006 Global Designer: IEEE Standardizes SystemVerilog - EDN17 Jan 2006 Cadence to Help Russian Electronics Industry - EE Times16 Jan 2006 Leakage Takes Priority at 65nm - EE Times12 Jan 2006 DFM and Low-power Design Will Dominate the Back End - Electronic Design12 Jan 2006 Cadence Claims X Architecture Boosts Net Good Die Per Wafer by a Minimum of 10% - DigiTimes06 Jan 2006 Portable Design Announces 2005 Editor's Choice Award Products - Portable Design06 Jan 2006 EDA Vendors Eye Consumer Market - EE Times02 Jan 2006 EDA execs: ESL, DFM will stand out in lackluster '06 - EE Times01 Jan 2006 Executive Roundup: What 2006 Has in Store - Semiconductor International