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08 Sep 2015 Head in the Clouds -

06 Aug 2015 How IoE Will Alter Supply Chains - Semiconductor Engineering06 Aug 2015 5 Things To Know About The IoT - Semiconductor Engineering05 Aug 2015 Cadence tool yields faster power analysis for SoC design - EDN Europe05 Aug 2015 RTL platform enables accurate power use analysis - Electronic Specifier04 Aug 2015 The Indago Debug Platform can improve verification productivity up to 50% - Electronics Maker04 Aug 2015 Realtek accelerates SoC verification with the Palladium XP platform - Electronic Specifier04 Aug 2015 Realtek accelerates system-on-chip verification with Cadence Palladium XP Platform - Connecting Industry

31 Jul 2015 Who's Calling The Shots - Semiconductor Engineering30 Jul 2015 Top 15 Integrating Points In The Continuum Of Verification Engines - Semiconductor Engineering30 Jul 2015 Which Process, Material, IP? - Semiconductor Engineering30 Jul 2015 Securing EDA In The Cloud - Semiconductor Engineering30 Jul 2015 Making Hardware Design More Agile - Semiconductor Engineering30 Jul 2015 USB Connectors Get Smarter - Semiconductor Engineering30 Jul 2015 IP Verification Challenges - Semiconductor Engineering28 Jul 2015 A tiny chip that can save lives - The Times of India27 Jul 2015 Advanced WEBENCH tools for expert power-supply designers - EDN23 Jul 2015 System Design Enablement - Looking Beyond the Chip20 Jul 2015 Cadence and UltraSoC debug IP for Xtensa - Electronics Weekly20 Jul 2015 UltraSoC to debug heterogeneous Tensilica processors - EE Times Europe15 Jul 2015 PSpice builds interfaces to PCB and system-level cosimulation - Tech Design Forum14 Jul 2015 Lip-Bu Tan talks about the challenges and opportunities facing the EDA sector - New Electronics09 Jul 2015 Divide And Conquer: A Power Verification Methodology Approach - Semiconductor Engineering09 Jul 2015 Speeding Up Analog - Semiconductor Engineering09 Jul 2015 Cloud 2.0 - Semiconductor Engineering09 Jul 2015 Tale Of Two Hls Viewpoints - Semiconductor Engineering08 Jul 2015 Voice recognition software optimised for Cadence Tensilica Fusion - Electronic Specifier08 Jul 2015 Formal Verification For Post-Silicon Debug - Semiconductor Engineering06 Jul 2015 How Much Security Is Enough? - Semiconductor Engineering

30 Jun 2015 India could be a bigger design centre than US - Electronics Weekly26 Jun 2015 Finfet rival FD-SOI bigged up in European event - Electronics Weekly26 Jun 2015 Cadence CEO: More collaboration and engagement - EE Times India25 Jun 2015 CEO interview: Cadence is about enablement, collaboration - EE Times Europe25 Jun 2015 Asynchronous' Impact On Tools - Semiconductor Engineering25 Jun 2015 More Data, Different Approaches - Semiconductor Engineering25 Jun 2015 EDA's Clouded Future - Semiconductor Engineering25 Jun 2015 Towards A Metric To Measure Verification Computing Efficiency - Semiconductor Engineering25 Jun 2015 What Is A System Now? - Semiconductor Engineering24 Jun 2015 Cadence & Applied Materials to optimise the planarization process - Electronic Specifier24 Jun 2015 Interoperable Application-Specific Solutions For Formal Verification - Semiconductor Engineering23 Jun 2015 Cadence and Applied Materials collaborate on joint development program - Connecting Industry17 Jun 2015 Power Verification Now Required - Semiconductor Engineering16 Jun 2015 Consolidation And Innovation - Semiconductor Engineering16 Jun 2015 Reducing The Risk Of Third Party IP Integration - Semiconductor Engineering16 Jun 2015 Analog's Day Of Reckoning - Semiconductor Engineering16 Jun 2015 IP Integration Challenges Increase - Semiconductor Engineering16 Jun 2015 Managing Dynamic Power - Semiconductor Engineering16 Jun 2015 SoC Integration Headaches Grow - Semiconductor Engineering15 Jun 2015 Mentor, Cadence Join Forces - Semiconductor Engineering15 Jun 2015 Formal Low-Power Verification Of Power-Aware Designs - Semiconductor Engineering14 Jun 2015 Startup plans neural network front-end for sensor systems - EE Times Europe12 Jun 2015 Implementation system certified on 16nm FinFET process - Electronic Specifier10 Jun 2015 Dac 2015: Day 3 - Semiconductor Engineering10 Jun 2015 Cadence collaborates with TSMC on IoT subsystem - Electronic Specifier10 Jun 2015 TSMC adds Cadence and Imagination subsystems for IoT - Tech Design Forum09 Jun 2015 Cadence combines its own, and acquired Jasper, formal tools - EDN Europe09 Jun 2015 TSMC certifies Cadence Innovus Implementation System on 16-nanometer FinFET Plus Process - Connecting Industry09 Jun 2015 Full Coverage Or Full Monty? - Semiconductor Engineering08 Jun 2015 Reduce verification schedule by up to three months - Electronic Specifier08 Jun 2015 Implementation & signoff portfolio certified for 14nm process - Electronic Specifier08 Jun 2015 Formal verification platform upgrade said to bring x15 performance boost - New Electronics08 Jun 2015 Formal integration enhances bug-hunting for Cadence - Tech Design Forum08 Jun 2015 Cadence implementation and signoff tools certified on Intel Custom Foundry 14nm process - Connecting Industry08 Jun 2015 Cadence synthesis engine delivers 5x faster turnaround time - EE Times India08 Jun 2015 Cadence implementation and signoff tools certified on Intel Custom Foundry 14nm process - Connecting Industry

28 May 2015 Full Coverage Or Full Monty - Semiconductor Engineering28 May 2015 What's Different At 16/14Nm? - Semiconductor Engineering27 May 2015 Portfolio shortens design cycle & improves predictability - Electronic Specifier27 May 2015 Thermal simulation package boosts EDA connectivity for advanced thermal management - EDN Europe27 May 2015 Automating Root-Cause Analysis To Reduce Time To Find Bugs By Up To 50% - Semiconductor Engineering26 May 2015 Tortuga Logic: Hardware Security - Semiconductor Engineering26 May 2015 Ideas for improved protocol debug - EE Times Asia24 May 2015 Cadence updates Allegro with PCB production and routing tools - Tech Design Forum22 May 2015 Cadence strengthens Allegro technology portfolio to make design cycles shorter and more predictable - Connecting Industry21 May 2015 30-year-old OrCAD goes for usability - EDN Asia21 May 2015 Cadence updates Allegro with PCB documentation revisions - EDN Europe21 May 2015 How Hard Is Fd-Soi Design? - Semiconductor Engineering18 May 2015 Vehicle ethernet adds to IP virtual reference kits for board design - Tech Design Forum15 May 2015 Making DAC'a must' for designers - Tech Design Forum14 May 2015 Power Management Verification Requires Holistic Approach - Semiconductor Engineering14 May 2015 How Do We Push The Limits Of Power? - Semiconductor Engineering14 May 2015 Trouble Ahead For IP Industry? - Semiconductor Engineering14 May 2015 Accelerating Development For LP - Semiconductor Engineering13 May 2015 USB 3.0 host IP offers 40% lower dynamic power consumption - Electronic Specifier13 May 2015 How To Achieve Optimal Ppa And Up To 10X Tat Gain In Your Next Digital Design Implementation - Semiconductor Engineering07 May 2015 Cadence Tensilica HiFi DSPs get optimised Conexant voice/speech processing - EDN Europe07 May 2015 DSPs feature smart audio software for real-world conditions - Electronic Specifier07 May 2015 Challenges For The IoT - Semicondutor Engineering

30 Apr 2015 Fortune taps Cadence Designs as great place to work - It's Your Business30 Apr 2015 PCB Tools, Part 1: Zuken, Mentor, Cadence, Altium - EDA Caf�29 Apr 2015 Debug platform is 50% faster than competing devices - Electronic Specifier29 Apr 2015 SoC debug tool offers improved productivity, better system insights - EDN Europe29 Apr 2015 Cadence Introduces Indago Debug Platform - Chip Design Magazine28 Apr 2015 Cadence debug tool handles root-cause data - Electronics Weekly28 Apr 2015 Cadence upgrades debug for system-level era - Tech Design Forum28 Apr 2015 Boosts your debugging productivity by 50% says Cadence - EE Times23 Apr 2015 Cadence Introduced The New Tensilica Fusion DSP - Chip Design Magazine23 Apr 2015 DSP targets IoT & wearable SoCs - Electronic Specifier23 Apr 2015 Cadence expands OrCAD PCB portfolio with new products and technologies to enable faster product creation - Connecting Industry23 Apr 2015 Products & feature updates added to CAD portfolio - Electronic Specifier23 Apr 2015 A tool speeds FinFET design - EE Times Europe23 Apr 2015 Cadence/Tensilica shapes DSP IP for low-energy SoC implementations - EE Times Europe23 Apr 2015 Pressure Builds To Revamp The Design Flow - Semiconductor Engineering23 Apr 2015 Is Art Acceptable In Verification? - Semiconductor Engineering23 Apr 2015 What Not To Verify - Semiconductor Engineering23 Apr 2015 What Eda's Big 3 Think Now - Semiconductor Engineering23 Apr 2015 Blurring The Lines On Prototyping - Semiconductor Engineering23 Apr 2015 How Health And Auto Requirements Drive Iot Design - Semiconductor Engineering22 Apr 2015 DSP core set to meet IoT, wearables processing requirements - New Electronics22 Apr 2015 Fusion core targets voice-activated devices - Tech Design Forum22 Apr 2015 A fusion DSP for IoT - EE Times Europe22 Apr 2015 Meeting Functional Safety Requirements Efficiently Via Electronic Design Tools And Techniques - Semiconductor Engineering14 Apr 2015 New low power processors offer robust security features and high memory efficiency - Connecting Industry10 Apr 2015 Cadence digital and custom/analog tools achieve TSMC certification - Connecting Industry09 Apr 2015 Fighting Dark Silicon With Specialized Hardware - Semiconductor Engineering09 Apr 2015 UPF 3.0 Moves Toward Ratification - Semiconductor Engineering09 Apr 2015 Is Dark Silicon Wasted Silicon? - Semiconductor Engineering09 Apr 2015 The Wild West Of Automotive - Semiconductor Engineering09 Apr 2015 Stacked Die, Phase Two - Semiconductor Engineering09 Apr 2015 Does Fast Simulation Help Debug Productivity? - Semiconductor Engineering09 Apr 2015 Design tools achieve TSMC certification for 10nm FinFET - Electronic Specifier07 Apr 2015 Ecosystem Changes - Semiconductor Engineering07 Apr 2015 Ecosystem Changes - Semiconductor Engineering01 Apr 2015 Speech enhancement software adds noise suppression to DSPs - Electronic Specifier

31 Mar 2015 Demand for smaller & cheaper mixed signal technology - Electronic Specifier27 Mar 2015 Architecturally Optimizing Memory Bandwidth - Semiconductor Engineering27 Mar 2015 Innovus Implementation System claims up to 10� turnaround time reduction - EDN26 Mar 2015 System Design Enabling The Human Intranet - Semiconductor Engineering26 Mar 2015 Designs Getting Squeezed - Semiconductor Engineering24 Mar 2015 HLS is the New Black - EE Journal23 Mar 2015 Wild West: OneSpin's Dave Kelf rides shotgun on SystemC - EDA Caf�23 Mar 2015 Using Physically Aware Synthesis Techniques to Speed Design Closure of Advanced-Node SoCs - Systems Design Engineering19 Mar 2015 Cadence & ARM launch IP interoperability agreement - Electronic Specifier19 Mar 2015 Cadence/Intel collaboration yields 14nm library characterisation reference flow - EDN Europe19 Mar 2015 3D Effects At 20Nm And Beyond - Semiconductor Engineering19 Mar 2015 Cadence, ARM Ink IP Cross Licensing Agreement - Electronics 36019 Mar 2015 Cadence named one of best companies to work for - Binghamton Homepage18 Mar 2015 ARM & Cadence IP Partnership for Faster SoC Design - SemiWiki18 Mar 2015 Cadence, ARM sign 'broad IP interoperability agreement' - New Electronics18 Mar 2015 Cadence and ARM strategic partners on IP - EE Times Europe18 Mar 2015 ARM and Cadence agree to share IP access - Tech Design Forum17 Mar 2015 Cadence aims to speed design of big 14nm chips - Electronics Weekly16 Mar 2015 Design reaches out from the edge - Tech Design Forum13 Mar 2015 First Time Success And Cost Control - Semiconductor Engineering13 Mar 2015 Cadence Introduces Innovus Implementation System - Systems Design Engineering12 Mar 2015 Implementation system for complex SoC designs - Analog IC Tips12 Mar 2015 Thermal Is Still Simmering - Semiconductor Engineering12 Mar 2015 Where Did Auto Innovation Begin? - Semiconductor Engineering12 Mar 2015 Automotive Drives Novel Ip Demands - Semiconductor Engineering12 Mar 2015 Rethinking The Cloud - Semiconductor Engineering12 Mar 2015 The Interconnected Web Of Power - Semiconductor Engineering11 Mar 2015 Hdmi 2.0 Design And Verification Challenges - Semiconductor Engineering11 Mar 2015 Innovus: Cadence's Next Generation Implementation System - SemiWiki11 Mar 2015 SoC design package improves power, performance, area 'by up to 20%' - New Electronics11 Mar 2015 Cadence aims to recapture share of digital chip P&R with Innovus Implementation System - EDN Europe10 Mar 2015 Cadence Looks to Improve Position in Digital Design Tools - Electronics36010 Mar 2015 Cadence reworks implementation for both finFET and older processes - Tech Design Forum05 Mar 2015 Technology enables surround sound over any set of headphones - Electronics Specifier

27 Feb 2015 Brite Semiconductor improves quality of results and reduces time to market for four SoC designs - Connecting Industry27 Feb 2015 SerDes PHY for PCIe 2.0/3.0 achieves PCI-SIG compliance - EE Times India26 Feb 2015 Incremental Design Methodologies - Semiconductor Engineering26 Feb 2015 Partition Lines Growing Fuzzy - Semiconductor Engineering26 Feb 2015 First Time Success And Cost Control - Semiconductor Engineering26 Feb 2015 Getting The Right Return On Invested Power Consumption - Semiconductor Engineering26 Feb 2015 Processor Use Models Evolving - Semiconductor Engineering25 Feb 2015 2015 DesignCon - EDA Café25 Feb 2015 Cadence combines HLS tools in Stratus release - Tech Design Forum24 Feb 2015 Challenges Before 2.5D/3D Technology - Electronics For U24 Feb 2015 Object-based audio demands higher-performance audio processors - Tech Design Forum24 Feb 2015 High Level Synthesis Gets Stronger - SemiWiki22 Feb 2015 Cadence's Brad Griffin Digs Deep Into DDR - iconnect00721 Feb 2015 IoT Sensor Node Designs Call for Highly Integrated Flows - SemiWiki19 Feb 2015 How To Extend Litho Scaling - Semiconductor Engineering18 Feb 2015 Wrist watch GPS running monitors operate for up to 30 hours - Electronic Specifier16 Feb 2015 CDNLive Silicon Valley: last chance for early bird discount - Tech Design Forum12 Feb 2015 Reliability Definition Is Changing - Semiconductor Engineering12 Feb 2015 Who Pays For Eda Shift Left? - Semiconductor Engineering12 Feb 2015 The Art Of Lp Analog - Semiconductor Engineering12 Feb 2015 With Responsibility Comes Power - Semiconductor Engineering12 Feb 2015 Emulation Uses Increase - Semiconductor Engineering12 Feb 2015 Power Management Verification Requires Holistic Approach - Semiconductor Engineering12 Feb 2015 Postcards From The Edge (Of The Cloud) - Semiconductor Engineering12 Feb 2015 The Lp R&D Ecosystem - Semiconductor Engineering11 Feb 2015 Leveraging Physically Aware Design-For-Test To Improve Area, Power, And Timing - Semiconductor Engineering11 Feb 2015 A Prototyping with FPGA Approach - Systems Design Engineering10 Feb 2015 Software-Driven Verification - Semiconductor Engineering10 Feb 2015 Processor enables IoT sensor hub IC - Electronic Specifier10 Feb 2015 Perform verification tasks twice as fast - Electronic Specifier05 Feb 2015 SoC dev't environment supports ARM premium mobile IP suite - EE Times India05 Feb 2015 Electronics Industry Voices Doubts - Communications Today05 Feb 2015 Fd-Soi Meets The Iot - Semiconductor Engineering05 Feb 2015 Development environment for ARM premium mobile IP suite announced - Electronic Specifier05 Feb 2015 Cadence 2014 Results - SemiWiki04 Feb 2015 Energy-efficient, comprehensive media components for mobile market - Connecting Industry03 Feb 2015 Cadence provides efficient media components to mobile market - Electronic Specifier02 Feb 2015 Back To The Future - Semiconductor Engineering

29 Jan 2015 First Look: 10Nm - Semiconductor Engineering29 Jan 2015 Automotive System Design Challenges - Semiconductor Engineering29 Jan 2015 What Will 2015 - Bring For System-On-Chip Verification?29 Jan 2015 Extended design portfolio speeds creation & analysis - Electronic Specifier29 Jan 2015 Cadence's processor selected for use in IoT WiFi chips - Electronic Specifier29 Jan 2015 Chinese IoT Firm Makes Wireless-MCUs Around Xtensa - Electronics36029 Jan 2015 Tools And Flows In 2015 - Semiconductor Engineering29 Jan 2015 Cadence sol'ns speed up design signoff, compliance check - EE Times India29 Jan 2015 Handling 20nm Design Challenges - Electronics For U28 Jan 2015 Cadence updates Sigrity tools and license options - Tech Design Forum27 Jan 2015 Sigrity Focuses on LPDDR4 Compliance Analysis in 2015 Release - SemiWiki26 Jan 2015 Signoff tools reduce 28nm SoC time to tapeout by 33% - Electronic Specifier22 Jan 2015 Manufacturing And Packaging Changes For 2015 - – Semiconductor Engineering22 Jan 2015 Building a high-performance, low-power audio/voice subsystem - Embedded Computing Design21 Jan 2015 UMC and Cadence collaborate to deliver 28nm design reference flow - Connecting Industry21 Jan 2015 1.7-GHz ARM Cortex-A7 draws only 200-mW of dynamic power - EE Times Europe16 Jan 2015 Higher Frequencies Mean More Memory - Semiconductor Engineering15 Jan 2015 Processors provide 75% better local memory area - Electronic Specifier15 Jan 2015 What Will Change In Design For 2015? - Semiconductor Engineering15 Jan 2015 Unraveling Power Methodologies - Semiconductor Engineering15 Jan 2015 Designing For Automotive - Semiconductor Engineering15 Jan 2015 New Challenges For Wearables - Semiconductor Engineering15 Jan 2015 Customizable IP for High-Performance, Low-Power Audio Subsystems - SemiWiki14 Jan 2015 Productivity And The Iot - Semiconductor Engineering14 Jan 2015 Tensilica processors enter their 11th generation - EE Times Europe14 Jan 2015 Processors promise local memory power efficiency - EE Times India14 Jan 2015 Extensible processor IP offers up to 75% memory power and area savings - EDN14 Jan 2015 Cadence updates Xtensa with memory and power saving features - Tech Design Forum14 Jan 2015 Low-Power Audio/Voice Subsystems Using Customizable Dsp Blocks And Audio Interface Ip - Semiconductor Engineering13 Jan 2015 HiFi Sounds Better than Ever - SemiWiki13 Jan 2015 Comment: let's move chip design a little to the left - Electronics Weekly09 Jan 2015 EEsof EDA software links to Cadence Virtuoso for RFIC co-design - EDN Europe08 Jan 2015 DSP IP core for SoC 32-bit audio/voice processing - Electronic Specifier08 Jan 2015 Towards object-based audio with Tensilica's 4th-gen HiFi DSP Architecture IP - EDN Europe06 Jan 2015 Compiler drastically reduces design time for complex transport system - Electronic Specifier06 Jan 2015 Design tools complement 28nm Super Low Power process to achieve 2.0GHz performance - Electronic Specifier06 Jan 2015 Fourth Generation Cadence Tensilica HiFi DSP Core Supports Emerging MultiChannel Object-Based Audio - John Day's Automotive Electronics06 Jan 2015 High-Level Synthesis Uncovers PPA Tradeoffs of Various Hardware Accelerators - Electronic Design