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May

17 May 2012 IPC-2581 Consortium Validates Bare Board Fab Data - Printed Circuit Design & FAB14 May 2012 Netronome reduces SoC power use with timing tricks - EE Times14 May 2012 Top 10 Tips for Success with Formal Analysis – Part 3 - EE Times09 May 2012 Cutting Edge Technologies Lead Nominations for American Technology Awards - Tech America Foundation06 May 2012 Forte Design Systems joins Cadence Connections program - EE Herald02 May 2012 Cadence Expands OrCAD Capture Marketplace - Gabe on EDA02 May 2012 TripleCheck IP validator from Cadence for IP compliance testing - EE Herald01 May 2012 How to Pick the Best Verification IP for Your Application - Chip Design Magazine
 
April

30 Apr 2012 Hierarchical methods for power intent specification - EETimes16 Apr 2012 Building Predictability Into Your Low-Power Design Flow - EE Times10 Apr 2012 Cadence has design flow for SMIC 40nm process - Electronics Weekly05 Apr 2012 "Selling System-Level Design" - System-Level Design Community03 Apr 2012 Opinion: What Comes After Power Intent Formats? - EE Times
 
March

30 Mar 2012 Cadence CEO Lip-Bu Tan Honored with Singapore Award - Chip Design Magazine30 Mar 2012 Extending the Metric-Driven Verification Methodology to TLM Featured - SOC Central28 Mar 2012 Slideshow: EE Times, EDN honor 2012 ACE Award winners - EE Times26 Mar 2012 Cadence supports development of the cloud - EE Times26 Mar 2012 Cadence introduces LPDDR3 memory IP solution - EE Times22 Mar 2012 Cadence unveils high-performance, low-power design IP to support LPDDR3 memory standard - EE Times Europe21 Mar 2012 Cadence expands Shanghai office and R&D center - Silicon Valley/San Jose Business Journal19 Mar 2012 Building a NAND flash controller with high-level synthesis - EE Times14 Mar 2012 What’s The Difference Between Software Development Platforms? - Electronic Design13 Mar 2012 Cadence TSMC, ARM call for more collaboration - EE Times13 Mar 2012 Alberto Sangiovanni-Vincentelli receives EDAA Lifetime Achievement Award - EE Times13 Mar 2012 CDNLive: the Keynotes - SemiWiki08 Mar 2012 Shoot the Engineer - Low-Power Engineering Community08 Mar 2012 Flexibility Vs. Portability In Emulation - Low-Power Engineering Community08 Mar 2012 Avoiding Chip Melt - Low-Power Engineering Community07 Mar 2012 Issues in IP - YouTube06 Mar 2012 Cadence reveals latest RTL to GDS flow - EE Times06 Mar 2012 Cadence offers design support to Australia's IC startups - EE Times05 Mar 2012 Cadence moves physical design software to 20-nm - EE Times02 Mar 2012 Cadence Says A Plus Is Complexity Curve - Investor's Business Daily01 Mar 2012 Komplexe Architekturen im Griff - EE24.net
 
February

13 Feb 2012 Power Intent Formats: Light at the End of the Tunnel? - EE Times09 Feb 2012 Virtual LP - Low-Power Engineering Community09 Feb 2012 Corporate citizenship challenge on Saturday - The Hindu06 Feb 2012 Good 2011 Results for Cadence - Gabe on EDA02 Feb 2012 Cadence a billion dollar company once again - EE Times01 Feb 2012 Cadence: Q4, Q1 View Beat; Year View Beats; Op Margin Improves - Barron's
 
January

30 Jan 2012 Top 10 Tips for Success with Formal Analysis – Part 2 - EE Times24 Jan 2012 The Art Of Double-Indirect Sales And Product Marketing - System-Level Design Community20 Jan 2012 Experts At The Table: Making Software More Energy-Efficient - Low-Power Engineering Community17 Jan 2012 New Book “Advanced Verification Topics” published by Cadence - EE Times12 Jan 2012 Experts At The Table: Making Software More Energy-Efficient - Low-Power Engineering Community12 Jan 2012 Rethinking Good Enough - Low-Power Engineering Community12 Jan 2012 The Next Big Challenge - Low-Power Engineering Community12 Jan 2012 When Worlds Collide: Saving Power In Communications Applications - Low-Power Engineering Community12 Jan 2012 Status Report: Power-Aware Design Flow - Low-Power Engineering Community12 Jan 2012 Making Software Better - Low-Power Engineering Community11 Jan 2012 Cadence expands proven NAND Flash design IP offering - Components in Electronics10 Jan 2012 Speeding up FLASH - EE Journal09 Jan 2012 Cadence Memory Controller and PHY IP Supports ONFI 3 - EDA Blog