Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
About Cadence
> Newsroom
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Newsroom
ARM and Cadence have recently announced the tape out of the industry’s first 20nm design based on the ARM Cortex™-A15 MPCore™ processor. The test chip, targeting TSMC’s 20nm process, was jointly developed by engineers from ARM, Cadence and TSMC using a Cadence RTL-to-signoff flow. The milestone announcement is the result of an 18 month collaboration between ARM and Cadence on optimized design flows for the Cortex-A15 processor.
Read more
»
08 Feb 2012
Cadence President and Chief Executive Officer Lip-Bu Tan to Present at the Morgan Stanley Technology, Media & Telecom Conference
06 Feb 2012
Cadence Collaborates with Samsung Foundry to Deliver Design-for-Manufacturing Solution for 32-, 28- and 20-Nanometer Chip Design
01 Feb 2012
Cadence Reports Fourth Quarter and Fiscal Year 2011 Financial Results
17 Jan 2012
Cadence Publishes Definitive Book on Advanced Verification for Today's ICs
09 Jan 2012
Cadence Expands Proven NAND Flash Design IP Offering with ONFI 3 PHY and Controller
06 Jan 2012
Cadence Announces Fourth Quarter and Fiscal year 2011 Financial Results Webcast
13 Dec 2011
Cadence Palladium XP Verification Computing Platform Speeds Deployment of Panasonic Systems-on-Chip for Digital Consumer Products
Read more press releases
»
02 Feb 2012
Cadence a billion dollar company once again
-
EE Times
30 Jan 2012
Top 10 Tips for Success with Formal Analysis – Part 2
-
EE Times
24 Jan 2012
The Art Of Double-Indirect Sales And Product Marketing
-
System-Level Design Community
20 Jan 2012
Experts At The Table: Making Software More Energy-Efficient
-
Low-Power Engineering Community
17 Jan 2012
New Book “Advanced Verification Topics” published by Cadence
-
EE Times
12 Jan 2012
Experts At The Table: Making Software More Energy-Efficient
-
Low-Power Engineering Community
12 Jan 2012
Rethinking Good Enough
-
Low-Power Engineering Community
Read more news
»
Press Releases
In The News
Third-Party Press
Cadence Articles
Newsletters
Multimedia Center
Media Contacts
Nancy Szymanski
Cadence Design Systems, Inc.
408.473.8382
nancy@cadence.com
Dean Solov
Cadence Design Systems, Inc.
408.944.7226
dsolov@cadence.com
Media contacts
»
Cadence Fact Sheet (PDF)
2010 Annual Report