Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions for:
Advanced Node
Enterprise Verification
Hosted Design
Low-Power
Mixed-Signal
System Development
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology and Technology Adoption
Design Collaboration
Talent Development
Programs
Startup Acceleration
VCAD
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Offerings
Training Course Catalogs
Support & Training Home
Programs and Initiatives
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
ASIC Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
News and Events
Newsroom
Multimedia Center
Events and Webinars
Company Info and Resources
Investor Relations
Executive Team
Cadence Research Laboratories
Community Involvement
Customer Success
Careers
Media Gallery
Contact Us
About Cadence Home
Home
>
About Cadence
> Newsroom
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Del.icio.us
Digg
Slashdot
Technorati
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Newsroom
Cadence and GLOBALFOUNDRIES Technology Agreement
As part of a wide-ranging, multi-year software and services agreement, Cadence is providing GLOBALFOUNDRIES with a wide array of products, solutions and services...
Read more
»
Cadence Co-Founder Honored by IEEE and Royal Society of Edinburgh
Dr. Alberto Sangiovanni-Vincentelli received the 2009 IEEE/RSE Wolfson James Clerk Maxwell Award for his pioneering research in the field of electronic design automation (EDA).
Read more
»
16 Nov 2009
Cadence Announces Expanded SoC Design Alliance with Toshiba Corporation
04 Nov 2009
Exar Selects Cadence as Mixed-Signal EDA Provider
03 Nov 2009
Cadence Marks Annual Innovation Day with Honors for its Top Technology Leaders
02 Nov 2009
Hitachi Achieves Test Compression Levels Four Years Ahead of Industry (ITRS) Roadmap by Leveraging Cadence OPMISR Compression Technology
29 Oct 2009
SMIC and Cadence Announce the Availability of 65-Nanometer Low power Reference Flow 4.0
28 Oct 2009
Cadence Reports Q3 2009 Financial Results
27 Oct 2009
Silicon Hive Utilizes Cadence Palladium III Solution for Highest Quality IP for Multi-Core Multi-Million Gate Designs
Read more press releases
»
28 Oct 2009
Outlook 2010 : It’s a Mixed-Signal World
-
New Electronics
24 Oct 2009
Cadence and ARM joining hands to develop SoC design flow
-
EE Herald
14 Oct 2009
Technology and entrepreneurship — Click on three areas to fire up growth
-
The Hindu Business Line
12 Oct 2009
Roundtable: Virtualization & Simulation
-
EDACafe
06 Oct 2009
Systems Design and Verification Platforms – The Best Is Yet to Come
-
Chip Design Magazine
30 Sep 2009
Yet to Come
-
Chip Design Magazine
29 Sep 2009
Openness and Cooperation Create Healthy EDA Ecosystem
-
EDN
Read more news
»
Press Releases
In The News
Third-Party Press
Cadence Articles
Newsletters
Multimedia Center
Media Contacts
Carolina Noguera Binstadt
Vice President
Text100
415.593.8429
#nacadence@text100.com
Nancy Szymanski
Cadence Design Systems, Inc.
408.473.8382
nancy@cadence.com
Media contacts
»
Cadence Quarterly Industry Analyst Newsletter (PDF)
Cadence Fact Sheet (PDF)
2008 Annual Report (PDF)