Please join us on our Technology on Tour: Club-System Verilog events in Sophia Antipolis and Eindhoven.
This is a great opportunity for you to meet and network with verification users, share experiences, ideas, insights and gather information on the best available verification solutions from Cadence.Event details
The event will focus on UVM SystemVerilog and other technologies and methodologies (such as VIP, Metric-Driven Verification, SystemVerilog and low power), the new trends in the industry and hands-on details that can help you to increase your verification productivity.
Key Cadence R&D, Application Engineers and product management representatives will share their latest development work and future directions and will provide you the opportunity for a lot of Interactive and one-on-one discussions with the experts.Who should attend
If you are a verification manager, VLSI director or project manager, it is a great opportunity to come, bring your Verification Team and sharpen their skills and knowledge.If you are a verification and/or design engineer using SystemVerilog and/or Verification IP, this is THE event you should attend. Register Today Agenda
||SystemVerilog Roadmap + Tips and Tricks |
||SystemVerilog / UVM Debug (incl. Incisive Debug Analyzer)|
||UVM Standard Update + UVM Multi-Language|
||VIP + Interconnect Validator|
||Low Power Verification (incl. CPF/UPF)|