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 Technology on Tour: System Verilog Events

 
Type:
Cadence Event
Date:
Multiple Dates  
Location:
Multiple Locations  

01 Oct 2013 - Sophia Antipolis, France       [ Register ]
03 Oct 2013 - Eindhoven, The Netherlands       [ Register ]

Please join us on our Technology on Tour: Club-System Verilog events in Sophia Antipolis and Eindhoven.
This is a great opportunity for you to meet and network with verification users, share experiences, ideas, insights and gather information on the best available verification solutions from Cadence.

Event details
The event will focus on UVM SystemVerilog and other technologies and methodologies (such as VIP, Metric-Driven Verification, SystemVerilog and low power), the new trends in the industry and hands-on details that can help you to increase your verification productivity.

Key Cadence R&D, Application Engineers and product management representatives will share their latest development work and future directions and will provide you the opportunity for a lot of Interactive and one-on-one discussions with the experts.

Who should attend
If you are a verification manager, VLSI director or project manager, it is a great opportunity to come, bring your Verification Team and sharpen their skills and knowledge.If you are a verification and/or design engineer using SystemVerilog and/or Verification IP, this is THE event you should attend.

Register Today

Agenda
08:30 Registration
09:00 Welcome
09:30 SystemVerilog Roadmap + Tips and Tricks
10:45 Break
11:00 SystemVerilog / UVM Debug (incl. Incisive Debug Analyzer)
12:00 Lunch
13:00 Simulation Performance
14:00 UVM Standard Update + UVM Multi-Language
14:30 VIP + Interconnect Validator
15:30 Break
15:45 Low Power Verification (incl. CPF/UPF)

Dates and Locations
01 Oct 2013 - Sophia Antipolis, France       [ Register ]
03 Oct 2013 - Eindhoven, The Netherlands       [ Register ]

Questions About this Event?
Send email to marketing_euro@cadence.com