Home > About Cadence > Events > Event Series

 Cadence Technology on Tour: Custom IC - Analog IP Verification Seminar

 
Type:
Technology on Tour
Date:
Multiple Dates  
Location:
Multiple Locations  

07 Oct 2014 - Eindhoven, The Netherlands       [ Register ]
08 Oct 2014 - Duesseldorf, Germany       [ Register ]
09 Oct 2014 - Bracknell, United Kingdom       [ Register ]
10 Oct 2014 - Edinburgh, United Kingdom       [ Register ]
13 Oct 2014 - Dresden, Germany       [ Register ]
14 Oct 2014 - Milan, Italy       [ Register ]
15 Oct 2014 - Grenoble, France       [ Register ]

Best practices and methodologies for verifying DAC/ADCs and PLLs with SPICE accuracy in minutes and hours

How do you verify the functionality of your data converters (ADCs and DACs) and PLLs against performance specifications? You’ll need to consider your architecture, impact of advanced technology nodes, device noise, post-layout parasitic, device mismatch, and design integration.

This full-day seminar featuring technical presentations will help to tackle your verification challenges. You’ll get an overview of data converter and PLL design architecture, plus learn best practices, verification plans, methodologies, and techniques using the production-proven Cadence® Spectre® simulation technologies in the Virtuoso® Analog Design Environment (ADE). You’ll gain invaluable insight from our analog IP designers and simulation technology R&D experts on how to verify today’s complex data converters and PLL designs more productively and profitably. Topics covered include:

  • Design specification-driven simulation
  • Linear phase-domain modeling
  • Efficient Spice accurate and high-performance simulation
  • Metastability characterization
  • Effective number of bits (ENOB) verification

Agenda
09.00 – 09.30Registration
09.30 – 09.35Introduction to ADC and PLL Verification Seminar
09.35 – 10.15ADC architectures and examples
Verification considerations for an ADC
10.15 – 11.00ENOB verification planning and execution for a SAR ADC
  • Transient SINAD
  • Dynamic Comparator Characterization
  • Capacitor DAC Characterization
  • Clock Generator Characterization
11.00 – 11.15Break
11.15 – 12.15ADC Verification
  • Best practices with AMS Designer and Spectre XPS
12.15 – 12.45Physical Design Effects
  • Demonstration of parasitic-aware methodologies for analysis of a key ADC block, including Parasitic Estimates flow and Virtuoso Layout Suite for Electrically Aware Design
12.45 – 13.45 Lunch
13.45 – 14.30 PLL Modeling and simulation
  • Block Design Considerations
  • Phase Domain Modeling of PLL components
  • PLL closed-loop Phase Noise Simulations
14.30 – 15.15PLL Verification
  • Best practices with AMS Designer and Spectre XPS
15.15 - 15.45 Physical Design Effects
  • Demonstration of Voltus-Fi EM/IR flow for analysis of a key PLL block
15.45 - 16:00Wrap-up

Dates and Locations
07 Oct 2014 - Eindhoven, The Netherlands       [ Register ]
08 Oct 2014 - Duesseldorf, Germany       [ Register ]
09 Oct 2014 - Bracknell, United Kingdom       [ Register ]
10 Oct 2014 - Edinburgh, United Kingdom       [ Register ]
13 Oct 2014 - Dresden, Germany       [ Register ]
14 Oct 2014 - Milan, Italy       [ Register ]
15 Oct 2014 - Grenoble, France       [ Register ]

Questions About this Event?
Send email to marketing_euro@cadence.com