Address your most complex SoC verification challenges in this free, full-day seminar
Learn proven and validated metric-driven verification methodologies to improve your overall productivity.
Verification has evolved into a complex project that often spans multiple teams including digital, analog, and mixed signal, but the discontinuity associated with multiple, incompatible methodologies among design teams has limited productivity. The Universal Verification Methodology (UVM) addresses verification complexity and interoperability across languages and throughout the electronics industry for both novice and advanced teams while also providing consistency. In this seminar, you will learn about the breadth of verification technology Cadence has today in the Incisive Enterprise Solution and the new technologies we are bringing to you shortly.
This seminar is designed for any engineers and/or technical managers who are interested in having better visibility and predictability in the overall verification process.What you will learn:
Space is limited. Register now!
- Cadence SoC verification solution
- Core improvements in simulation performance. e/Specman verification, UVM, and debug
- Integrated verification IP (VIP), formal, and simulation solutions
- Innovative advanced debug and metric driven verification technologies
Dates and Locations
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