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Technology on Tour: PCB System Design and Implementation

Cadence Event  
10 Apr 2014  
Cadence Office, Bracknell, UK  

What you will discover

During this free technical seminar, Cadence® application engineers will, through presentations and numerous live demonstrations, outline the front-to-back design process from initial system design to layout and manufacturing. You’ll learn about implementing high-speed interfaces (e.g. DDR3), analysis of their system performance, and their integration into large FPGAs. You’ll gain insights into designing with the latest versions of Cadence® Allegro® Design Entry HDL / OrCAD® Capture CIS, Allegro PCB Designer (including the High Speed and Miniaturization options), Allegro FPGA System Planner, and the new Allegro Sigrity™ signal integrity and power integrity solutions.

Who should attend?
  • Electronic circuit designers
  • Signal integrity engineers
  • Power integrity engineers
  • PCB layout designers
  • Design managers
09:00 - 09:30 Registration
09:30 - 09:45 Welcome and Introduction
09:45 - 10:45 System Definition and Feasibility
10:45 - 11:00 Break and Networking
11:00 - 12:30 Physical Implementation
12:30 - 13:30 Lunch and Networking
13:30 - 15:00 System Performance Verification
15:00 - 15:15 Break and Networking
15:15 - 15:45 Design Signoff
15:45 - 16:00 Q&A

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