best practices and gain valuable insight from Cadence mixed-signal technology experts. The focus of the day is predictable analog and mixed-signal through comprehensive integration of chip design flows to minimize design and verification loops. We’ll explain how the new technologies in Virtuoso 6.1.6, Encounter 13.1, Sigrity 12.0 and Incisive 13.1 releases can be applied to create mixed signal designs with better performance, lower power and in a shorter design window.Discover
the latest analog & mixed-signal methodologies and techniques, including:
- Analyze DFM effects (WPE, LOD/STI etc.) as soon as devices are placed – without the need to have LVS clean layout.
- Understand on how the electrical aware design flow (EAD) helps you analyze Rs & Cs and electromigration hazards simultaneously as the layout shapes are drawn.
- Model and simulate parasitics of signals passing from chip, through package onto PCBs in an integrated flow.
- Special considerations of 20nm/16nm design with FinFETs, local interconnect and double patterned masks.
- Correct by construction layout – with on-line DRC, LVS and constraint checking in both interactive & assisted chip layout.
- When to use analog IP blocks and when to design yourself.
case studies of how design teams are successfully using Cadence analog and mixed-signal IC solutions to achieve their tapeout goals, optimize performance and power, reduce development costs, and improve turnaround time.development costs, and improve turnaround time.Don't miss
this opportunity to resolve your design challenges and network with other expert users and Cadence technologists.Who should attend?
- AMS and SoC verification engineers
- Circuit designers
- Analog/custom layout engineers
- CAD engineers and managers
- Design managers
- Anyone involved with realizing analog and mixed-signal designs in silicon
|08:45 – 09:30
||Registration & Coffee|
|09:30 – 09:40
||Welcome and Opening remarks|
|09:40 – 11:20
||Electrically Aware interconnect design & managing transistor layout dependent effects|
|11:20 - 11:40
||Coffee break and networking|
|11:40 – 12:20
||Mixed signal Verification – it’s all about the interfaces|
|12:20 – 13:00
||Analog IP – Case study of Analog IP block; Cadence IP overview|
|13:00 - 13:45
|13:45 – 14:10
||Introduction to Custom at 20nm/16nm:- Design with FinFET, managing local interconnect & double patterning|
|14:10 – 15:40
||Correct by Construction layout in Virtuoso 6.1.6 – constraints, Modgens, In-Design DRC & layout assistance tools|
|15:40 – 16:20
||Chip/Package/Board integrated analog/RF design flows including Sigrity PowerSI field solvers|
|16:20 – 16:30
Questions About this Event?Send email to firstname.lastname@example.org