Home > About Cadence > Events > Archived Webinars

Archived Webinars 

Technology  Clear Filter

Date  Details  Technology  
25 Aug 2014
Archived Webinar: Addressing the Challenges of 16nm FinFET with Cadence Silicon Signoff and Verification Solutions
Watch this webinar to learn how Cadence’s silicon signoff and verification solutions can help you meet the challenges of designing for the 16nm FinFET process.
Event details »
System Design and Verification, Manufacturability Signoff, Advanced Node
22 Jul 2014
Addressing MCU Mixed-Signal Design Challenges for SoCs and IoT
Join this webinar, presented by ARM and Cadence, to learn ways to address Internet of Things (IoT) and system-on-chip (SoC) design and verification challenges using high-efficiency ARM® Cortex®-M0 processors, optimized physical and system intellectual property (IP), and an integrated mixed-signal design flow based on the Cadence® Virtuoso® platform.
Event details »
Custom IC Design, Analog/Mixed-signal Design, Mixed-Signal
17 Jul 2014
Introducing the Protium Rapid Prototyping Platform: Early, Pre-Silicon Software Development, Throughput Regressions, and High-Performance System Validation Recorded Webinar
This webinar shows how the Protium™ platform can be incorporated into your verification process for early, pre-silicon software development, throughput regressions, and high-performance system validation so you can get to market faster.
Event details »
System Design and Verification
14 Jul 2014
ARMv7 and ARMv8 Based Accelerated System Development Recorded Webinar
In this webinar we demonstrate a comprehensive flow on how to optimize and accelerate hardware and software development for ARM®-based systems.
Event details »
System Design and Verification, System Development
08 Jul 2014
Tapping Into High-Level Synthesis for Improved Time to Market, Quality of Results, and IP Reuse Recorded Webinar
Learn how HLS is being used to achieve 10X more productivity, 5X faster verification speed and better effectiveness, and 20% better Quality of Results in terms of area, performance, and power. You'll also learn how HLS helps to deliver the promise of IP reuse by designing at a higher level of abstraction.
Event details »
Functional Verification, System Development, Verification IP
12 Jun 2014
Archived Webinar: PTC Windchill ECAD Data Management in a Cadence Allegro TDO Environment
Learn techniques to bring multi-user schematic block-level management into your hierarchical design environment in this free webinar presented by PTC and Cadence.
Event details »
PCB Design
13 May 2014
Webinar: New Productivity Enhancements in Cadence Allegro AMS Simulator
Learn ways to boost your PCB design productivity in our upcoming webinar about productivity enhancements in Cadence® Allegro® AMS Simulator.
Event details »
PCB Design
09 Apr 2014
Archived Webinar: Addressing MCU Mixed Signal Design Challenges
Learn how ARM® high-efficiency processors and optimized physical and system IP, coupled with Cadence Virtuoso integration solution, enable customers to reduce time to market, realize power, performance and area design targets, and most importantly, satisfy the ever-increasing competitive market demands.
Event details »
Custom IC Design, Analog/Mixed-signal Design, Mixed-Signal
19 Mar 2014
Archived Webinar: Optimizing Your Verification Process with Incisive vManager Solution
Attend this webinar to learn how Cadence’s Incisive® vManager™ verification planning and management solution, along with metric-driven verification methodology, can help you accelerate your verification process. Learn more about the solution, which supports multiple users, analytics, projects, and engines.
Event details »
System Design and Verification, Functional Verification
12 Feb 2014
Archived Webinar: Effective System-Level Coverage Use Cases for Functional Verification
Attend this webinar to learn how you can extend coverage verification techniques to sub-system and system levels with hardware-assisted verification. You’ll also gain insight into new coverage use models that are being applied at the system level. This webinar will showcase customer case studies involving system-level coverage.
Event details »
System Design and Verification, Functional Verification
11 Feb 2014
Archived Webinar: Improving Quality and Time-to-Market for TSMC 16nm FinFET Process Using the Cadence Certified Tools and Flow
TSMC and Cadence have collaborated on a design infrastructure for the 16nm FinFET (16FF) process technology for more than a year. Attend this webinar to learn about the ongoing certification program targeting V1.0 completion, and how Cadence has delivered digital and custom design reference flows and V0.5 certified tools for TSMC’s 16FF process. For early adopters looking to design new devices based on FinFET requirements, TSMC and Cadence have the design infrastructure ready to address all challenges in 16nm design from digital and custom through signoff.
Event details »
Digital Implementation, Custom IC Design, Advanced Node Design, 3D-IC
12 Dec 2013
Archived Webinar: Testing the Testbench
Attend this webinar to learn more about how you can enhance the quality of your testbenches through unit testing. Hannes Froehlich, a Cadence solution architect, will provide tips and teach you how to run unit tests with Cadence Incisive Enterprise Simulator.
Event details »
System Design and Verification, Functional Verification
11 Dec 2013
Archived Webinar: Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
Join Cadence at 9:00am PST on Wednesday, December 11, 2013, for an informative webinar on two methodologies to migrate low-power verification from simulation to emulation.
Event details »
System Design and Verification, Functional Verification, Low-Power Design, Low-Power
13 Nov 2013
Archived Webinar: Efficient, Exhaustive Register Map Validation
This webinar will share how verification apps ease the adoption of powerful formal verification technology, previously the domain of a handful of formal verification experts. The presenter will overview the range of applications that package this powerful technology and put it in the hands of verification engineers without deep formal expertise. He will then focus on the register validation problem, and how the register validation app achieves rapid exhaustive verification, giving clear real-world examples.
Event details »
System Design and Verification, Functional Verification
30 Oct 2013
Archived Webinar: Leveraging SystemVerilog Real Number Modeling for Mixed-Signal SoC Regressions
Watch this webinar to see how Cadence is leveraging the IEEE P1800-2012 (SV) standard to provide behavioral modeling solutions to customers. In addition, learn how you can achieve a significant speed-up in simulation performance (greater than 100X – 500X) by replacing the analog portions of your design with functionally equivalent RNM using real/wreal functionality in Verilog-AMS and/or SystemVerilog.
Event details »
System Design and Verification, Functional Verification, Analog/Mixed-signal Design, Mixed-Signal
18 Sep 2013
Archived Webinar: Routing Interfaces Quickly and Efficiently on PCBs - Part 2
Ideal for PCB designers and ECAD managers, this webinar will provide techniques on accelerating routing of high-speed interfaces like DDRx, PCI Express, and SATA using new auto-interactive and improved interactive routing technology in the Cadence® Allegro® PCB Designer solution.
Event details »
PCB Design
12 Sep 2013
Archived Webinar: Accelerate PCB Routing by Optimizing FPGA Pin Assignments
This webinar will show you how you can shorten PCB routing time by optimizing FPGA pin assignments during layout. The session will demonstrate how you can propose FPGA pin assignments based on FPGA vendor rules to shorten routing time and potentially reduce PCB layer counts. This capability is enabled by Cadence® Allegro® FPGA System Planner working as an engine inside Cadence Allegro PCB Editor.
Event details »
PCB Design
05 Sep 2013
Archived Webinar: Accelerate MMMC Timing Closure with Physically Aware Timing Optimization Using Tempus Timing Signoff Solution
In this webinar, you’ll learn how the new Cadence Tempus Timing Signoff Solution addresses the impending challenge of performing analysis and optimization across large numbers of timing views.
Event details »
Custom IC Design, Manufacturability Signoff, Front-end Closure
04 Sep 2013
Archived Webinar: Best Practices in Verification Planning
This webinar articulates a methodology for verification planning based on actual experience at Freescale Semiconductor. The verification planning process described in this session is streamlined for derivatives and comprehensive enough for new design and verification development. It explains a complete verification flow including verification strategy, planning, change management, and closure.
Event details »
Functional Verification
29 Aug 2013
Archived Webinar: HDMI 2.0 Specification Highlights and Cadence Verification IP
HDMI 2.0 promises to deliver a whole new experience with increased bandwidth for higher resolution display screens. Find out more about this new standard and how you can use Verification IP to speed your design effort.
Event details »
Functional Verification, Verification IP
21 Aug 2013
Archived Webinar: Achieve Faster Timing Closure with Tempus Timing Signoff Solution
The new Cadence Tempus Timing Signoff Solution addresses both performance and capacity by leveraging massively parallelized computation across many CPUs. In this webinar, you’ll learn more about the motivation behind the Tempus solution, as well as its innovative technology and benefits.
Event details »
Manufacturability Signoff
25 Jul 2013
Archived Webinar: Analog Behavioral Modeling and Model Generation
This webinar covers behavioral modeling challenges and introduces real number models for functional behavioral modeling.
Event details »
Analog/Mixed-signal Design
17 Jul 2013
Archived Webinar: Configurable Specman Messaging for Improved Productivity
In this webinar we will expose previous shortcomings and reflect how the new infrastructure solves those issues.
Event details »
Functional Verification
28 Jun 2013
Archived Webinar: Introduction to M-PCIe
M-PCIe (Mobile PCI Express) is the latest generation of the PCI Express standard, targeted for the low-power requirements of mobile platforms, particularly Wi-Fi, graphics and applications processors. Cadence was one of the initial sponsors of M-PCIe. This talk explains what M-PCIe is, what applications will use it, how it differs from PCI Express, and what Cadence has to offer for M-PCIe.
Event details »
Verification IP
26 Jun 2013
Archived Webinar: Simplify UVM Debug with Cadence Incisive SimVision
This webinar walks you through the advantages of using the debug power of the Cadence Incisive SimVision unified graphical debugging environment within a complex, class-based SystemVerilog environment for both interactive and post-process debug. We will showcase some of the new SimVision enhancements that improve overall debug productivity.
Event details »
Functional Verification
25 Jun 2013
Archived Webinar: 6 Must-Know Tips to Optimize LPDDR and Wide I/O Performance
Should your next design incorporate LPDDR3 or Wide I/O? Should you leapfrog to LPDDR4 or Wide I/O 2? How would this impact your controller and PHY implementation? The most successful mobile products combine higher performance with lower power dissipation. Memory subsystem design is key to delivering both, but the implementation choices are not always clear. Watch this 30-minute, pre-recorded webinar today to get some answers and learn the six must-know tips to optimize LPDDR and Wide I/O performance.
Event details »
Design IP, Verification IP
20 Jun 2013
Archived Webinar: Reducing MCAD Iterations with STEP
This webinar will show how to view changes proposed by mechanical, how to import STEP models for components and enclosures designers in Allegro, OrCAD PCB Designer. It will also show how to export the PCB assembly in STEP format from Allegro, OrCAD PCB Editor.
Event details »
PCB Design
19 Jun 2013
Archived Webinar: Introducing Low-Power Verification RAK (Rapid Adoption Kit)
This webinar walks you through the power format file using the example design provided in the RAK, and outlines the implicit logic inferred from the power intent file. You’ll also see a demo of the latest Cadence low-power verification debug applied to the example, and learn how to download the RAK for your own use.
Event details »
Functional Verification, Low-Power
13 Jun 2013
Archived Webinar: Routing Interfaces Quickly and Efficiently on PCBs
Join us for a webinar to see how you can accelerate routing of high-speed interfaces like DDRx, PCI Express, and SATA using new auto-interactive and improved interactive routing technology within the Cadence® Allegro® PCB Design solution.
Event details »
PCB Design
23 May 2013
Archived Webinar: A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence Tools
Interested in advanced node designs? Enhance your expertise with two new webinars from TSMC and Cadence. Learn about how in-design design rule checking (DRC) and double patterning technology (DPT) checking can improve productivity; how to efficiently manage coloring data in front-to-back custom design flows; how local interconnect layers are supported within the Cadence Virtuoso platform and TSMC’s 20nm process technology and the Cadence methodology to support this process.
Event details »
Advanced Node
09 May 2013
Archived Webinar: Introducing UVM Multi-Language Open Architecture
This webinar explains the challenges of existing “quick stich” solutions and the requirements driving the new open source solution. During the session, you’ll learn about technical details including a demonstration of the work completed to date by Advanced Micro Devices (AMD) and Cadence. This collaborative effort has achieved an important milestone that the architects from both companies are ready to introduce and for which they are ready for feedback.
Event details »
System Design and Verification
25 Apr 2013
New TSMC-Cadence Webinars for Advanced Node Design: Addressing Layout-Dependent Effects
Interested in advanced node designs? Enhance your expertise with two new webinars from TSMC and Cadence. Learn about the TSMC Custom Design Reference Flow 3.0, jointly developed by Cadence and TSMC to provide a complete layout-dependent effect (LDE) flow for circuit and layout designers working at 28nm and below.
Event details »
Advanced Node Design
19 Feb 2013
Archived Webinar: USB 3.0 - Verification Challenges and Solutions
The USB protocol family is more important than ever with growing adoption of SuperSpeed USB (USB 3.0) and new USB protocols coming on line. However, these new capabilities have increased the difficulty of verifying USB designs. Cadence will present an overview of the challenges associated with verifying USB designs and methods for addressing those challenges with Verification IP (VIP).
Event details »
Functional Verification, Verification IP
13 Feb 2013
Archived Webinar: Challenges and Solutions for 20nm-and-below Custom Design
As custom designs move to the advanced process nodes of 20nm and below, one of the major challenges designers are grappling with is variation and its effects on the design. Variation manifests itself primarily in two ways: layout-dependent effects (affecting both the designer and the layout engineer), and variation that occurs because of new layout techniques that must be employed in a sub-20nm design. This webinar will introduce you to the ways that new Virtuoso technology is helping the industry overcome the challenges of custom design at complex nodes.
Event details »
Custom IC Design, Advanced Node Design
11 Dec 2012
Archived Webinar: ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with “ABVIP”
To achieve first-pass success, the sophistication of ARM ACE-based designs must be matched by a comprehensive verification approach. This webinar will show how formal and assertion-based verification techniques, combined with assertion-based verification IP (ABVIP), can be used in concert with popular UVM testbench VIP.
Event details »
Functional Verification
05 Dec 2012
Archived Webinar: Variation-Aware Design: Detecting and Fixing Layout-Dependent Effects using the Virtuoso Platform
In this webinar, you'll see how advanced Virtuoso technologies can help you detect and fix LDE problems by rapidly producing layout and verification results that feed the industry's first LDE-aware design flow. Learn how to fine-tune the corrections necessary to make sure LDE problems don't stop you from getting your design manufactured on time.
Event details »
Custom IC Design, Advanced Node
04 Dec 2012
Archived Webinar: Better Verification Performance – The Ideal Holiday Gift
Cadence is constantly developing new capabilities to improve verification performance. This webinar will dig deeper and describe more substantial changes you can make that will also lead to larger performance gains throughout the compile/elaboration, execution, and debug cycle.
Event details »
Functional Verification
27 Nov 2012
Archived Webinar: SimVision Simplifies UVM SystemVerilog Macro Debug
This webinar will introduce the user to the latest in macro debug capabilities offered within the SimVision debug solution. Users of UVM-based environments, where macros are heavily utilized, will find this webinar particularly useful. Join this webinar to learn how new functionality in SimVision can help you reduce your debug time significantly.
Event details »
Functional Verification
15 Nov 2012
Archived Webinar: Speed Verification Turnaround by Extending MDV to TLM
This webinar outlines an approach that extends today’s metric-driven verification methodologies up to TLM to verify functionality at the highest level at which it is introduced, speeding overall design and verification turnaround.
Event details »
System Design and Verification
14 Nov 2012
Archived Webinar: Variation-Aware Design: Efficient Design Verification and Yield Estimation
In this webinar, we’ll show you how to use advanced capabilities, such as worst-case corners and high-sigma yield analyses, to efficiently cover the design space and estimate design yield.
Event details »
Custom IC Design, Advanced Node
13 Nov 2012
Archived Webinar: UVM Sequences: Best Practices for Efficiency and Reuse
One of the primary goals of the UVM is to reduce the cost and burden of writing tests. This is accomplished by providing an abstract test definition interface in the form of sequences. Subsequently, much of the complexity involved with driving and monitoring the DUT is absorbed in UVM verification components (UVCs). This webinar will use the UVM Reference Flow so that you can recreate everything you learn in your own environment.
Event details »
Functional Verification
07 Nov 2012
Archived Webinar: Variation-Aware Design: Understanding the “What If” to Avoid the “What Now”
In this webinar, we will define variation, how it affects design performance, and what you can do to analyze, understand, and limit these effects. We’ll demonstrate how you can use sensitivity analysis to identify devices and design parameters that impact circuit performance, and how to use sensitivity analysis results to tune and improve design robustness.
Event details »
Custom IC Design, Advanced Node
06 Nov 2012
Archived Webinar: Integrating Chip Verification into an ISO26262 Traceability Flow
This webinar will show how to combine a metric-driven verification flow typically used in functional verification with an ISO26262 requirements management flow. The solution entails electronically transferring requirements into the verification flow, and then managing the verification effort independently from there.
Event details »
Functional Verification
25 Oct 2012
Archived Webinar: UVM SystemVerilog in a Multi-Language SoC World: UVM-ML
While the Accellera Systems Initiative UVM standard is defined for SystemVerilog, its architecture can support multi-language verification environments. Every SoC has some mix of models coded to IEEE and ANSI language standards. With 4 years of experience in OVM and UVM production verification environments, and 10 years of eRM expertise, Cadence has developed a set of open-source reference libraries and best practices for implementing multi-language UVM. This webinar will use the Cadence UVM multi-language (UVM-ML) contribution on UVMWorld.
Event details »
Functional Verification
16 Oct 2012
Archived Webinar: 5 Steps to Your First Power Shutoff (PSO) Verification
The 5 steps outlined in this webinar provide a proven approach that both reduces the effort to verify a PSO domain while also increasing the quality of the resulting design. This webinar uses the Incisive Verification Kit (supplied with each Incisive Enterprise Simulator XL installation) so that you can recreate everything you learn in your own environment. The example can also serve as a model and reference for your own first PSO implementation and verification.
Event details »
Functional Verification
10 Oct 2012
Archived Webinar: Accelerate Your Verification Debug with the New Incisive Debug Analyzer
Debug is a major bottleneck, consuming more than 50% of the overall verification effort for many engineers. In our Incisive® 12.2 release, Cadence introduces a new and innovative debug environment—Incisive Debug Analyzer—that provides a unique multi-language debug solution for comprehensive IP and SoC-level verification.
Event details »
Functional Verification
25 Sep 2012
Archived Webinar: Combining the Best of Both in an MDV Flow – Simulation and Formal
There exist many benefits to simulation technology within a metric-driven verification (MDV) flow, and an equal number of benefits using formal technology. Now users can combine these metrics together to take advantage of the best in each.
Event details »
Functional Verification
18 Sep 2012
Archived Webinar: Is SystemVerilog the Future of Analog Modeling?
A significant speed-up in simulation performance can be achieved by replacing the analog portions of a design with functionally equivalent real-number models using real/wreal functionality in Verilog-AMS and/or SystemVerilog to achieve a 100–500x performance boost for top-level SoC verification.
Event details »
Functional Verification
11 Sep 2012
Archived Webinar: No More Wrappers – New Interface Between e and SystemC TLM 2.0
Transaction-level models (TLMs) can be used in a number of ways to speed up the design and verification effort for SoCs and their software layers. The last several years has seen strong adoption of SystemC TLM 2.0 for high-level modeling; it has become the de-facto standard for such models.
Event details »
Functional Verification
21 Aug 2012
Archived Webinar: Why Debug at the Signal Level When SystemVerilog Class-Based Debug is So Simple?
This webinar will walk users through the advantages of using the debug power of SimVision within a complex class-based SystemVerilog environment for both interactive and post-process debug.
Event details »
Functional Verification
08 Aug 2012
Archived Webinar: Formal Apps to Automate Mainstream Verification Challenges
This webinar will show how technology and methodology can be packaged into “apps” that focus on high-value problems that are more efficiently solved using formal-based methods, and can be automated such that very little knowledge of formal or assertion-based verification (ABV) is required.
Event details »
Functional Verification
27 Jun 2012
Archived Webinar: Announcing – Incisive Metrics Center
In this webinar, we will introduce you to the new Cadence Incisive Metrics Center, a new and highly intuitive way to visually see what has been tested and what is left to test.
Event details »
Functional Verification
13 Jun 2012
Archived Webinar: What to Do When Code Coverage Closure Seems Impossible
In this webinar, we will show how new automation and methodology can help you easily sort “reachable” and “unreachable” code coverage holes.
Event details »
Functional Verification
23 May 2012
Archived Webinar: “Excellerating” UVM – Tuning Your UVM Environment for Maximum Performance
Get the details of what it takes to build an efficient UVM environment and how to tune an existing one. Learn best practices gleaned from the embedded applications space, where memory and speed are at a premium. After the webinar, numerous code examples will be available to you on cadence.com.
Event details »
Functional Verification
09 May 2012
Archived Webinar: Connecting SystemVerilog Real Numbers and Verilog-AMS Nets
This webinar will discuss the connection between these domains and how this enables analog block integration regardless of abstraction level (SPICE, AMS models, real number models). We will also discuss how to add to your verification quality and productivity using a metric-driven approach, which is enabled by this connection.
Event details »
Functional Verification
03 May 2012
Archived Webinar: Industry Leaders Unveil Shared Vision for 20nm – Cadence and IBM Present a Custom 20nm Solution
Analog and full custom design at 20nm will present a significant challenge for design engineers and layout designers. Layout-driven circuit design is a reality when considering layout-dependant effects (LDE) and dynamic coloring. Hear about addressing the challenges of 20nm design with double patterning–aware analog and custom blocks and IP. See a demonstration of dynamic coloring and hear about a 20nm design example from concept to tapeout.
Event details »
Custom IC Design, Manufacturability Signoff, Advanced Node
02 May 2012
Archived Webinar: Industry Leaders Unveil Shared Vision for 20nm – Cadence and Samsung Semiconductor Present a Digital 20nm Solution
Cadence and Samsung Present a Digital 20nm Solution. We will dig deep into the requirements for, and the technology behind, the ultimate in 20nm digital design and signoff. Get the inside scoop from industry leaders on their experiences, best practices, and recommendations for success.
Event details »
Digital Implementation, Manufacturability Signoff, Advanced Node
01 May 2012
Archived Webinar: Industry Leaders Cadence, TSMC, and ARM Outline their Vision for 20nm Silicon Success
In this webinar, ecosystem leaders will walk you through 20nm challenges and offer their experiences, guidance, and recommendations to help you gain clarity on how to succeed at advanced node design. Find out what it takes to enable foundry-optimized, higher-performance, lower-power designs at 20nm.
Event details »
Digital Implementation, Custom IC Design, Manufacturability Signoff, Advanced Node
25 Apr 2012
Archived Webinar: Maximizing Your Investment in the UVM Reference Flow
This webinar will focus on demonstrating the technical aspects of the UVM Reference Flow such that users can begin to use this new environment to improve their verification productivity.
Event details »
Functional Verification
10 Apr 2012
Archived Webinar: The Verification IP Behind the Cloud Technology Revolution
This webinar features Verification IP components that are driving server, storage, and networking companies to adopt emerging standards helping deliver the cloud computing infrastructure. Compute, networking, and storage resources make up the backbone of the cloud, and design and verification teams need cost-effective solutions that scale in response to real-time demands and product requirements.
Event details »
System Design and Verification, Functional Verification
10 Apr 2012
Archived Webinar: RTL-to-GDSII Low-Power Methodology
Attend this technical webinar and find out the latest Cadence Logic Design and Encounter Digital Implementation (EDI) System has to offer in enabling low-power designs. Learn how our intent-driven low-power methodology can significantly reduce power consumption while optimizing design team productivity and design cycle time. Meet power specifications no matter which technique you use: power shutoff, multiple supply voltages, dynamic voltage and frequency scaling, and others. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »
Logic Design, Digital Implementation, Advanced Node, Low-Power
05 Apr 2012
Archived Webinar: What is New in Encounter v11.1: Signoff Analysis
Attend this technical webinar and find out the latest Cadence Encounter Digital Implementation (EDI) System has to offer in enabling signoff and in-design signoff. Learn how the traditional timing, signal integrity, and power analysis signoff solutions have been enhanced to manage huge designs implemented on the most advanced process technologies. Maintain signoff accuracy for design methodologies that use double patterning; handle SoC designs with a growing number of operational modes more efficiently; and, enable efficient design flows that automate optimizations from floorplanning through pre-tapeout signoff. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »
Logic Design, Digital Implementation, Advanced Node, Low-Power
04 Apr 2012
Archived Webinar: How to Avoid Low-Power Failures
This webinar will share the details of what metrics matter during the different stages of low-power verification and implementation, and review how these metrics can be leveraged to reduce the risk of failures in your design. Knowing where to start and how to finish is fundamental to verification success. This webinar will focus more on methodology than tools; however, some tool-based representative examples will be shown for credibility and reference to the methodology.
Event details »
Functional Verification
29 Mar 2012
Archived Webinar: What is New in Encounter v11.1: Giga-Scale Design
Attend this technical webinar and find out the latest Cadence Encounter Digital Implementation (EDI) System has to offer in enabling giga-scale designs. Learn how our GigaFlex technology can handle growing capacity requirements by extending FlexModels, FlexILMs, and FlexViews. FlexModels enable netlist compression while retaining the relevant physical and logical information, allowing for faster turnaround time and one-pass implementation handoff. FlexILMs and FlexViews enable concurrent top-and block-level optimization and final hierarchical closure, resulting in fewer iterations and a faster path to hierarchical convergence. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »
Logic Design, Digital Implementation, Advanced Node, Low-Power
27 Mar 2012
Archived Webinar: What is New in Encounter v11.1: 20nm Design
Attend this technical webinar and find out the latest Cadence Encounter Digital Implementation (EDI) System has to offer in enabling 20nm designs. Learn about our new 20nm double-patterning digital implementation and signoff methodology. Get ready for the next step in process manufacturing evolution and create faster, smaller, more integrated devices. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »
Logic Design, Digital Implementation, Advanced Node, Low-Power
22 Mar 2012
Archived webinar - What is New in Encounter v11.1: High-Performance GHz+ Design
Attend this technical webinar and find out the latest Cadence Logic Design and Encounter Digital Implementation (EDI) System has to offer in enabling high-performance GHz and low-power microprocessor-based SoCs. Meet your power, performance, and area targets with physical synthesis and physical implementation technologies such as our GigaOpt optimization engine and clock concurrent optimization (CCOpt). CCOpt users are realizing up to 10% boosts in timing closure and up to 30% improvements in power and area. Enhance your productivity, time to market, and competitive advantage. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »
Logic Design, Digital Implementation, Advanced Node, Low-Power
07 Mar 2012
Archived webinar - Incisive Debug Message Analysis
The SmartLog is a new message analysis tool that allows for more advanced analysis of messages/SDMs in the user environment. Users can find related transactions, filter based on time/scope, message text, view source code snippets, and see full attribute information on recorded SDM transactions.
Event details »
Functional Verification
23 Feb 2012
Archived webinar - Racing for the Checquered Flag – Tuning Incisive for Speed
This webinar will share the operational information about how to tune a verification environment for peak performance. While knowing how to do this on individual tests will speed each run, larger potential gains can be achieved with metric-driven verification and its ability to optimize your overall functional verification plan.
Event details »
Functional Verification
15 Dec 2011
Archived webinar - Simplifying Code Coverage Analysis: Automatically Separating the Wheat from the Chaff
In this webinar, we will show how new automation and a revolutionary “case-splitting” methodology can help you separate the wheat from the chaff—the “reachable” versus the “unreachable” code coverage holes. A demonstration will reinforce the concepts learned during the session.
Event details »
Functional Verification, Enterprise Verification
08 Dec 2011
Archived webinar - Advanced Technology to Verify Complex Mixed-Signal Designs
As the size and complexity of mixed-signal designs have grown, so has the verification task. Designers face the challenging task of verifying complex power, performance, and functionality specifications as well as validating analog and digital interactions over a broad range of operations. To accomplish this, new mixed-signal analysis and verification technology and techniques are required. Join this webinar to hear about many of these new analog/mixed-signal verification approaches.
Event details »
Low-Power, Mixed-Signal
07 Dec 2011
Archived webinar - Set Your UVM Runtime Phases to Maximum Power
This webinar will share the steps you need to determine if your UVC really needs runtime phases. If it does, the component is simpler to build and maintain. Assuming you are attending because you do need to apply them, the webinar will provide critical methodology guidelines to maximize the verification power you will derive from runtime phases and help you to avoid common pitfalls as you integrate your UVC into larger system verification environments.
Event details »
Functional Verification, Enterprise Verification
06 Dec 2011
Archived webinar - Power Integrity Challenges in Mixed-Signal Designs
How many times have you discovered unanticipated IR drop or electromigration problems in the power grids of your complex analog/mixed-signal designs? If the answer is yes even once, you may want to join us for a one-hour webcast session from the Cadence Mixed-Signal Design Webinar Series.
Event details »
Mixed-Signal
17 Nov 2011
Archived webinar - Quickly Find Data Transport Bugs with Formal Scoreboarding
“Scoreboards” have been used in advanced simulation testbench environments for years. In this webinar, we will show how this same concept can be implemented with formal verification tools. Consequently, you will see how to benefit from powerful formal analysis algorithms to automatically test data integrity and root out the spectrum of simple problems to extreme corner cases.
Event details »
Functional Verification, Enterprise Verification
10 Nov 2011
Archived webinar - Bringing Order to the Chaos of IC Design: Solutions for the SoC Era
This webinar will demonstrate how Methodics products can be used within the Cadence Virtuoso custom/analog flow, as well as with Verilog and VHDL-based designs, to ensure higher quality and productivity. Topics covered include constraint design, testbench management, documentation, version control, configuration management, data management and distribution to remote sites, and access control.
Event details »
Custom IC Design
03 Nov 2011
Archived webinar - What Metrics Matter - A User’s Perspective on Coverage
The webinar will share the details of what metrics matter during the different stages of verification and how these metrics can be leveraged to reduce the risk of failures in your design. Knowing where to start and how to finish is fundamental to verification success. This webinar will be mostly focused on methodology and not tools; however, some tool-based representative examples will be shown for credibility and reference to the methodology.
Event details »
Functional Verification, Enterprise Verification
20 Oct 2011
Archived webinar - Oceans of Expertise Connecting the UVM to Sea (C /C++/SC)
This webinar will share the steps you need to prepare, build, and debug the mixed-language verification environment. It will focus on the methodology for mixed-language environments, bringing the Incisive Enterprise Simulator into the discussion primarily to describe advanced debug techniques.
Event details »
Functional Verification, Enterprise Verification
13 Oct 2011
Archived webinar: Automate Assertion Generation for Simulation, Formal and Emulation Flows
In this webinar, Cadence and NextOp Software will show how assertion synthesis enables a progressive, targeted verification process, allowing design and verification teams to more easily uncover corner-case bugs, expose functional coverage holes, and increase verification observability. A demonstration will reinforce the concepts learned during the session.
Event details »
Functional Verification, Enterprise Verification
22 Sep 2011
Archived webinar: ViVA IC615 - See the New Graphing Technology
In this webinar you will see a demonstration of the new ViVA Qt Graph which is available in IC615. This has a powerful and intuitive use model, and provides a lot of flexibility in the display of your simulation results.
Event details »
Custom IC Design
15 Sep 2011
Archived webinar - Applying Digital Verification Methodologies to Analog Design
This webinar will discuss how to approach analog block integration regardless of abstraction level (Spice, AMS models, real number models) and how to increase your verification quality and productivity using a metric-driven approach.
Event details »
Functional Verification, Enterprise Verification
08 Sep 2011
Archived webinar - Ending the Debate - Apples or PC's? e or SystemVerilog?
With HVL standardization, the importance of consistent, open, and interoperable methodologies are more evident than ever, and verification engineers can finally freely choose. Just like choosing Apples or PCs, understanding the pros and cons of both languages will end your debate of which language to choose. This webinar will also technically compare and contrast UVM e and UVM SystemVerilog to assist you in choosing which language would best meet your verification needs.
Event details »
Functional Verification, Enterprise Verification
07 Sep 2011
Archived webinar - Moving Design and Verification to the Next Level with High-Level Synthesis
Designing and verifying at the transaction-level of abstraction has promised great productivity and time-savings benefits, but until recently this has been limited to datapath blocks. But recent breakthroughs in synthesis algorithms and growing understanding of how to use SystemC to express a wider variety of structures are dissolving that limitation.
Event details »
System Design and Verification
30 Aug 2011
FPGA-based prototyping is hard to do – or is it?
Almost every digital SoC, ASIC and ASSP is prototyped in FPGAs; sometimes as a high-performance verification platform, but most often to get a head-start in developing software for the SoC. No matter what the purpose though, it is difficult to do and it takes too much time and too much effort, to get the prototype up and running.But does it really have to be so hard?
Event details »
System Design and Verification
23 Aug 2011
Archived webinar - Finding the Bugs in Your UVM Haystack
This webinar will help you see how GUI-based debug can improve your productivity over embedded print statements enabling you to visualize your UVM class structure, data, transactions, and more. It will focus on the debug capabilities in SimVision that will help you find those bugs no matter where they are in the haystack of data.
Event details »
Functional Verification, Enterprise Verification
28 Jun 2011
Archived webinar - Cadence and IC Manage - IP Reuse and Parasitic-Aware Design Using Cadence Virtuoso Technologies and the IC Manage Global Design Platform
Technology experts from IC Manage and Cadence present the advancements in the area of custom IC design and verification, focusing on IP collaboration/reuse and parasitic-aware design.
Event details »
Functional Verification, Custom IC Design
23 Jun 2011
Archived webinar - Verifying and Modeling Registers Using the SystemVerilog UVM
Register modeling is critical for IP and SoC verification, as a large part of the stimulus relies on configurable modes and activation of these modes at all levels. This webinar comprehensively covers this subject and shows you how it’s done—from design to debug, execution to error handling.
Event details »
Functional Verification
16 Jun 2011
Archived webinar - Reuse Legacy VMM VIPs in the UVM in 6 Simple Steps
UVM is the new industry standard, yet your investment in VMM VIP is preventing you from joining the party. This webinar will provide an overview of the Accellera UVM-VMM interoperability library and present a 6-step process for how to integrate an existing VMM VIP into a UVM environment.
Event details »
Functional Verification
15 Jun 2011
Archived webinar - Accelerating Design-in of Xilinx FPGAs while Optimizing PCB Layout for Cost and Performance
In this one-hour webinar, you will see how Cadence Allegro FPGA System Planner and Allegro PCB Editor can be used seamlessly with the Xilinx PlanAhead design tool to shorten time to design-in large pin-count FPGAs and reduce PCB layer count.
Event details »
PCB Design
26 May 2011
Archived webinar - Creating Meaningful Verification Plans
How do you go about writing a plan? How do you know when your plan is complete? And finally, how do you reuse the plan? We’ll answer these questions and show you how to easily create meaningful verification plans using metrics and UVM-based technology that can be reused.
Event details »
Functional Verification
24 May 2011
Debugging Linux-based Systems on Multi-core SoCs
The explosion of demand for mobile computing devices such as tablets is creating time-to-market pressure on very complex design challenges such as multi-core software/hardware architectures. This trend is driving change in methodology for software development to enable earlier software development, shorter debugging of complex software/hardware scenarios, and earlier exploration of system architecture and performance. In this webinar we will explore the methodology for utilizing a virtual prototype for early software development particularly for multi-core systems, and the key capabilities required of a virtual prototype solution for building, debugging, and analyzing a complex system.
Event details »
System Design and Verification
17 May 2011
Archived webinar - Cadence and Altera: Helping You Accelerate System Realization
In this one-hour webinar, you will see how Cadence Allegro FPGA System Planner and Allegro PCB Editor can be used seamlessly with Altera’s Quartus II FPGA design tools to shorten time to design-in large pin-count FPGAs and optimize PCB layout.
Event details »
PCB Design
12 May 2011
Archived webinar - Verification 1-2-3 with Assertion-Driven Simulation
This is it: a simple, straightforward methodology that increases bug detection and produces much cleaner RTL. Totally revolutionary assertion-driven simulation will simulate, visualize, debug, and can be implemented with coverage.
Event details »
Functional Verification
21 Apr 2011
How to achieve system level functional coverage closure faster
With more and more software content in chips—embedded or application level—RTL design and verification is no longer the main bottleneck to a faster tapeout schedule. System integration, including embedded software development and verification are rapidly becoming the key areas to focus on with regard to cost and product delivery schedules.
Event details »
System Design and Verification
14 Apr 2011
Archived webinar - How to Successfully Verify Your Low-Power Designs
Low-power mandates have changed the way we verify silicon. We now need to test every combination and permutation comprehensively—but how? This webinar presents real issues with real answers and effective guidelines for successful low-power flows.
Event details »
Functional Verification, Low-Power Design
10 Mar 2011
2011 Functional Verification Webinar Series
Cadence verification experts are presenting a series of technical webinars on the most relevant topics in functional verification. In these concise, 1-hour sessions, our technical experts will address hot topics including the Universal Verification Methodology (UVM), low power, metric-driven verification (MDV), formal techniques, and mixed-signal verification approaches.
Event details »
Functional Verification
15 Dec 2010
Archived webinar - Magillem: Role of IP-XACT in TLM
Magillem is one of the leading suppliers of IP-XACT related tools. Listen to them as they talk about role of IP-XACT, how it applies to RTL and TLM level
Event details »
System Design and Verification
10 Dec 2010
Archived webinar - Metric-Driven Synthesis: Collecting and Leveraging Inter and Intra Synthesis-Run Statistics to Improve Quality of Results
This webinar details the specific classes of synthesis metrics that are most valuable to collect, and provides hands-on demo examples of how and why intelligently analyzing them can improve your synthesis productivity.
Event details »
Functional Verification, Logic Design
09 Dec 2010
Archived webinar - Are You Ready for Your Next-Generation Analog/Mixed-Signal Product?
Attend this webinar to learn how Triune Systems takes advantage of the Cadence mixed-signal tool suite for their nanoSmart ultra–low-power green technology development (National Science Foundation funded , NSF-SBIR Grant No. 1013282). In this webinar, we will talk about the Cadence mixed-signal design and verification solution, which enables the abstraction of analog and mixed-signal designs for both architectural exploration and verification. Triune Systems will talk about this technology and some of the techniques they employ with these tools to establish design confidence for meeting aggressive time-to-market goals.
Event details »
Custom IC Design, Analog/Mixed-signal Design
08 Dec 2010
Archived webinar - Migrating from VMM to the UVM
With the UVM 1.0 release around the corner, this is the time to plan a migration from OVM, VMM, and custom methodologies. The Accellera Verification IP Technical Subcommittee standardized an OVM-VMM interoperability Best Practices guide in July of 2009. Cadence has updated the library associated with the standard to be compatible with the UVM, and donated that back to Accellera. In addition, Cadence has upgraded the OVM-UVM migration script based on real-world customer experience. Attendees will learn about the migration planning requirements by walking through case studies of VMM and OVM migrations as well as Vera RVM to OVM/UVM. These examples will cover both the verification environment and the associated register packages.
Event details »
Functional Verification, Logic Design
08 Dec 2010
Archived webinar - Jeda Technologies: Performing Comprehensive Code and Functional Coverage on SystemC TLM Models
In this webinar, JEDA Technologies will present why it is necessary to perform code and functional coverage, and will discuss techniques available to do so. They will also share results on how coverage performed on C/SystemC models correlates with their RTL equivalents.
Event details »
System Design and Verification, Functional Verification
07 Dec 2010
Archived webinar - OpenPDK: What is the Goal of this Effort, and What is the Status?
The industry is calling for a "single source" for EDA enablement. Some solutions want to enforce a particular implementation of a PDK. But this forces the entire EDA industry to comply to the same format and, in most cases, retool to comply. The OpenPDK effort is very different. OpenPDK's goal is an implementation-free, single source for EDA enablement. OpenPDK members are seeking a means to define all of the necessary process information—design rules and device definitions—into a format that can be published once and used by all EDA vendors equally. Hear Cadence and Mentor discuss their views on the OpenPDK effort.
Event details »
Custom IC Design
06 Dec 2010
Archived webinar - Where Does Power Intent Come From? Create and Debug Power Intent for Low-Power Designs
This webinar will describe real problems experienced in today’s chip designs and how to create and debug power intent in your proven power verification flow.
Event details »
Functional Verification, Logic Design
03 Dec 2010
Archived webinar - When IP Collides, Brace for Impact on Timing Constraints and CDC! Verify and Manage Your Timing Constraints and CDCs!
This webinar will describe real problems experienced in today’s chip designs and describe a flow that provides an automatic means of avoiding chip failure.
Event details »
Functional Verification, Logic Design
02 Dec 2010
Archived webinar - IC 6.1: A Leap Forward in Productivity
Join us in this webinar to learn how the Cadence custom IC team took an innovative metrics-driven approach to delivering customer-proven productivity improvements in the Virtuoso 6.1 release. You will learn how to pinpoint inefficiencies in your flows, as well as some of the latest back-to-basics tips on boosting productivity.
Event details »
Custom IC Design
02 Dec 2010
Archived webinar - Silicon Diagnostics – Enabling Greater Accuracy for Fast Silicon Evaluation
Process variations are greatly complicating efforts to accurately locate design-process defects for timely and profitable production. This webinar will provide an overview of how advanced diagnostics capabilities enable a more productive, intuitive silicon diagnostics process.
Event details »
Functional Verification, Logic Design
01 Dec 2010
Archived webinar - Managing Parasitics in the Back End
this webinar, we will go through a methodology referred to as “Rapid Analog Prototyping” that shows how to efficiently and accurately generate physical information such as parasitics without having to wait for hand-crafted layout.
Event details »
Custom IC Design
01 Dec 2010
Archived webinar - Achieve the Next Level of Verification Productivity with the Specman Advanced Option
In this webinar learn about the new Specman Advanced Option that can improve your overall verification effort by 40–60%. Find out how to save hundreds of hours of simulation time using the dynamic load/re-seed capability, how to debug your e code with the performance of compiled code, and how to greatly increase productivity and system-level scalability by using the multi-core compilation capability.
Event details »
Functional Verification, Logic Design
01 Dec 2010
System-Level Simulation Acceleration with UVM/OVM
The Universal/Open Verification Methodologies have greatly streamlined the RTL verification process for SoCs. But at the same time, the amount of software necessary to integrate the SoC into a working device has exploded, making the software integration and debug problem the new bottleneck in delivering a working system.
Event details »
System Design and Verification
30 Nov 2010
Archived webinar - A Practical Guide to Exploiting Optimization in Custom Design Flows
This webinar will briefly explore the evolution of optimization in analog design and then quickly move on to how it is used in Virtuoso technology to provide real, practical benefits to analog designers. Attendees will learn about the expanded capabilities Cadence offers and how easy it is to incorporate optimization into the design flow. Also, practical guidance will be given on where optimization works well and how to use it as a design aid.
Event details »
Custom IC Design
30 Nov 2010
Archived webinar - How To Completely Eliminate SoC Connectivity Bugs (Really!)
Bugs from incorrect connectivity – whether they’re misconnected IP blocks inside an SoC or erroneous muxing of pad rings – can kill a chip as just easily as more sophisticated functional bugs. With internal connection points surpassing hundreds of thousands of nodes, the traditional approach of assigning detail-oriented summer interns to spot-check connectivity with some dynamic simulations is rapidly losing effectiveness. In this webinar, we’ll show you how to apply formal verification technology to exhaustively prove with 100% mathematical certainty that all of your SoC’s internal and external pad ring connections are completely correct.
Event details »
Functional Verification, Logic Design
19 Nov 2010
Archived webinar - Managing Parasitics in the Front End
This webinar features the Virtuoso Analog Design Environment GXL. Within the tool, there are facilities for you to add parasitic quantities to nets in the design, explore the effects on your measurements (including corners and statistics if you wish), and then give the implementation engineer direction on the critical nets within the design that need to be handled with care.
Event details »
Custom IC Design
18 Nov 2010
Archived webinar - Design Techniques That Make ECOs Predictable
This webinar will discuss how automated ECO synthesis works, discuss techniques for debugging ECO synthesis problems (large patch size, failure to close timing after ECO synthesis, failure to find a valid patch), and finally discuss implementation flows that make the automated ECO synthesis process predictable.
Event details »
Functional Verification, Logic Design
17 Nov 2010
Archived webinar - Analog Verification—How Do You Know Your Circuit is Right? Smart Verification!
The complexity of analog and RF ICs and SoCs, combined with increasing cost pressures, means it is critical for engineers to efficiently verify complex sets of performance and operating conditions. In this webinar, we will discuss the latest methodologies and techniques available from Cadence today to improve both verification productivity and design team collaboration.
Event details »
Custom IC Design
17 Nov 2010
Archived webinar - CoFluent Design: Creating the SystemC Models you Need, but Don't Have
In this technical webinar, CoFluent Design will share their knowledge on how to easily create SystemC transaction-level models (TLMs). They will present CoFluent Studio illustrating how to quickly create and analyze models for virtual prototyping, and to use these models in a pure SystemC or mixed-language environment with your existing Cadence simulator.
Event details »
System Design and Verification
16 Nov 2010
Archived webinar - Are You Losing Sleep Over How to Perform Top-Level Mixed-Signal SoC Verification?
This webinar will introduce you to the Cadence mixed-signal verification environment that enables full-chip verification very close to digital speeds using real number models. You’ll also learn about mixed-signal behavioral modeling using Real/Wreal functionality in Verilog-AMS and SystemVerilog to achieve 500x performance boost for top-level SoC verification.
Event details »
Functional Verification, Logic Design
15 Nov 2010
Archived webinar - New Techniques for Debugging NonEQs and Aborts in Equivalence Checking
This webinar will provide basic background knowledge on what equivalence checking is, how it works, and what causes false non-equivalence and aborts. We will then cover new techniques for debugging non-equivalence issues and preventing aborts in equivalence checking through coding style changes, implementation flows, and verification tool setup tips.
Event details »
Functional Verification, Logic Design
11 Nov 2010
Archived webinar - Maximizing Your Investment in the UVM
This webinar will demonstrate the technical aspects of the UVM Reference Flow so that users can immediately employ this new environment to improve their verification productivity. Emphasis will be on making sure users understand the design and verification components, how the book explains the theory and practical aspects behind the methodology and the reference flow examples, how to run the flow, and the legal responsibilities of users who decide to incorporate the UVM Reference Flow as part of their process.
Event details »
Functional Verification, Logic Design
11 Nov 2010
Archived webinar - Remote Enablement for a Globalized Workforce - Cadence and Open Text Enable Optimized Performance
Attend this technical webinar to find out how Cadence and OpenText are providing a complete solution and competitive edge for companies in four key areas: Accelerate design schedules and reduce time to market; Do more work in less time; Maximize resources while reducing cost; Manage outsourced design projects. This webinar will also cover the needs to enable OpenText’s Exceed onDemand and the Cadence Virtuoso software to work together for optimal performance to help customers achieve their high level objectives of virtualization, remote access, and collaboration.
Event details »
Custom IC Design
10 Nov 2010
Archived webinar - Parasitic-Aware Design: A Complete Analog Design Flow
This webinar will give you a high-level overview of the main steps involved in rapidly developing your designs and being able to deal with parasitics effectively. Each of the steps in the design, implementation, and verification of the circuits will be shown, and you will see a brief demonstration. This webinar will get you started with the proper background information to get the most out of the subsequent webinars. You will be introduced to the tools and methodology Cadence offers for parasitic-aware design analysis.
Event details »
Custom IC Design
09 Nov 2010
Archived webinar - Metric-Driven Verification: The Galaxy Beyond Just Simulation
Let us introduce you to the galaxy of MDV solutions beyond just RTL simulation. This webinar will show you how the proven MDV approach can help you successfully verify your entire SoC design, beyond the RTL-only scope from the past.
Event details »
Functional Verification, Logic Design
04 Nov 2010
Archived webinar - Switch Mode Power Supplies (SMPS)
This webinar features the use of Cadence PSpice technology to design and analyze switched-mode-power supplies.
Event details »
PCB Design, IC Packaging and SiP Design
03 Nov 2010
Archived webinar - TSMC Reference Flow 11: ESL Focus on High-Level Synthesis
This webinar will introduce the concepts of modeling for high-level synthesis and a repeatable approach to creating high-quality RTL designs that meet area, timing, and power constraints.
Event details »
System Design and Verification, Functional Verification
02 Nov 2010
Archived webinar - Why Cadence Has the Best UVM Solution
In this webinar, you’ll learn how to build a multi-language UVM environment including high-performance verification engines tuned for the UVM and advanced debug and analysis. Your productivity depends heavily on the solution you choose, and Cadence has the most experience with the UVM in the industry.
Event details »
Functional Verification, Logic Design
02 Nov 2010
Archived webinar - Increase Your Productivity and Profitability: A Deterministic Path to Silicon Realization
In this webinar you will see a new path combining the tools and visibility you need to work simultaneously and effectively, boosting productivity, predictability and profitability. With a predictable, repeatable path to closure, you'll develop higher quality silicon without sacrificing your cost goals. Attend this webinar if you are an engineer and engineering manager that cares about increasing productivity, and are facing challenges such as low power, mixed signal, Giga-gates/Gigahertz, global productivity and metrics, SiP co-design and verification.
Event details »
Functional Verification, Logic Design, Digital Implementation, Custom IC Design, PCB Design
21 Oct 2010
Archived webinar - DRC+ Now: Early DFM Signoff in the Digital Implementation Process
This joint technical webinar with GLOBALFOUNDRIES will describe what, when, why, and how designers can incorporate DRC+ into an existing digital implementation flow to achieve DFM signoff at 28nm and below. With Cadence pattern matching and automated fixing built into Encounter tools, designers can quickly identify and fix DRC+ errors, thereby avoiding potential manufacturability issues down the road. By capturing these issues early in the design flow, DRC+ provides Encounter place-and-route engineers peace of mind that their SoC design is DFM-clean.
Event details »
Digital Implementation, Manufacturability Signoff
20 Oct 2010
Archived webinar - DRC+ Now: Early DFM Signoff in the Custom Implementation Process
This joint technical webinar with GLOBALFOUNDRIES will describe what, when, why, and how designers can incorporate DRC+ into an existing analog, custom, or mixed-signal design flow to achieve DFM signoff at 28nm and below. With Cadence pattern matching and automated fixing built into Virtuoso tools, designers can quickly identify and fix DRC+ errors, thereby avoiding potential manufacturability issues down the road. By capturing these issues early in the design flow, DRC+ provides Virtuoso layout designers peace of mind that their layout and IP is DFM-clean.
Event details »
Digital Implementation, Manufacturability Signoff
20 Oct 2010
Archived webinar - System Realization Services from Cadence
Using real project examples, this webinar will highlight how customers are employing new methodology and technology for system design and verification, and the benefits of using Cadence products. It will also describe various ways that Cadence Services uniquely enable customer success and adoption of these new solutions.
Event details »
System Design and Verification, Functional Verification, Services
19 Oct 2010
Archived webinar - Linking the Business and Electronic Component Data Domains using PTC Windchill Gateway for Cadence Allegro Design Workbench
In this webinar, you will learn how to integrate electronic and business data environments to enable a live bi-directional feed of data and a superior parts management system, resulting in fewer design spins and fewer delayed projects.
Event details »
PCB Design, IC Packaging and SiP Design
14 Oct 2010
Archived webinar - Multi-Gigabit Serial Link Design and Analysis
Multi-gigabit serial links can make compliance and interoperability testing a challenging experience. This webinar provides an overview of the issues you’ll face when creating multi-gigabit serial links and will show you how Allegro PCB SI GXL can solve these problems.
Event details »
PCB Design, IC Packaging and SiP Design
07 Oct 2010
Archived webinar - Creating Complex HDI Designs Using the Allegro Constraint-Driven HDI Design Flow
Increasing the functional density while reducing design size through miniaturization techniques is a requirement for many of today’s PCBs and IC package designs. Learn how to set up a robust, constraint-driven PCB design flow with a comprehensive set of design rules for all different styles of high-density interconnect (HDI) designs, from a hybrid build-up/core combination to a complete build-up process like ALIVH.
Event details »
PCB Design, IC Packaging and SiP Design
06 Oct 2010
Archived webinar - TSMC Reference Flow 11 : ESL Focus on TLM Design and Verification Methodology
This webinar will introduce the various levels of abstraction in the stages of refinement and how to architect an advanced UVM verification environment to reuse through the entire flow.
Event details »
System Design and Verification, Functional Verification
30 Sep 2010
Archived webinar - Allegro PCB Signal and Power Integrity Analysis
Learn how to bring layout decisions (such as critical placement of components and net-level constraints) to the forefront of the design cycle. Allegro PCB SI tools can be used before and during schematic creation to develop rules on advanced interfaces. See how the constraint-driven PCB design flow improves collaboration among design groups, is proven to shorten the design cycle, and reduces or eliminates unnecessary prototype iterations.
Event details »
PCB Design, IC Packaging and SiP Design
29 Sep 2010
Archived webinar - Calypto: Application of Sequential Analysis for ESL Methodology Adoption
During this webinar, Calypto describes its shared vision and provides a complete overview of how its sequential analysis-based products play a key role in today’s new era of application-driven design.
Event details »
System Design and Verification
22 Sep 2010
Archived webinar - Imperas: Breaking New Ground in Embedded Software Development
This presentation will show how the integration of Incisive SystemC simulation, Incisive Software Extensions, processor models from OVP, and software simulation and verification tools from Imperas enables software functional verification.
Event details »
System Design and Verification
22 Sep 2010
Archived webinar - Complex Mixed-Signal PCB Design and Analysis with Allegro AMS Simulator
Discover the power of this full-featured analog and mixed-signal simulator, which supports everything from high-frequency systems to low-power IC designs. Learn about its advanced features, including Smoke analysis, Optimizer (including Curve Fit), Monte Carlo, Sensitivity, and Parametric Plot – and see how they can be applied for everyday analog and mixed-signal design issues.
Event details »
PCB Design, IC Packaging and SiP Design
15 Sep 2010
Archived webinar - CircuitSutra: Role of Standards in TLM Driven Design and Verification Methodology
In this presentation, we will talk about various SoC modeling standards and how they work with Cadence tools to enable the TLM-driven design and verification methodology.
Event details »
System Design and Verification
15 Sep 2010
Archived webinar - Predictable, Shorter Design Cycles for Dense, Complex PCBs
A growing number of large pin-count devices with shrinking BGA pin pitches, and increasing use of standards-based interfaces (PCI Express, Serial ATA, DDR3, etc.), are just a few things that are not only extending the design cycle time for dense, complex PCBs but also making them unpredictable. Learn how Allegro PCB Design can shorten your design cycles and make them more predictable so you can meet aggressive product launch windows and maximize profitability.
Event details »
PCB Design, IC Packaging and SiP Design
09 Sep 2010
Archived webinar - Maximizing the Performance-Per-Watt of Your Next Design
Attend this webinar to explore the different options available to you to reduce power from both a leakage and dynamic aspect. Techniques such as multiple threshold voltage optimization and clock gating strategies will be discussed, as well as more advanced power management options such as power shutoff, multiple supply voltages, and dynamic voltage/frequency scaling. Finally, we will also explore the use of cutting-edge techniques like dual/quad flops to help you streamline your chip’s performance like never before!
Event details »
Digital Implementation
08 Sep 2010
Archived webinar - XtremeEDA: The Importance of a Complete Methodology for ESL
This talk will look at a few of the reasons why ESL adoption has been slow, and show why a new approach using a holistic methodology is changing the rate of adoption.
Event details »
System Design and Verification
03 Sep 2010
Archived webinar - Should You Design Your Next System With 3D TSVs? Hear from GLOBALFOUNDRIES and Cadence
Attend this webinar to discuss the challenges associated with the design, implementation, and verification of 3D-ICs using TSVs. Learn about optimum packaging solutions to meet desired performance and cost goals. Run through a holistic, production-proven flow that allows you to complete your 3D-IC design quickly.
Event details »
Digital Implementation, 3D-IC
31 Aug 2010
Archived webinar - In-design Signoff; It's All About Getting It Right the First Time
Attend this webinar to discover how to make the complete design flow more efficient by enabling the same signoff functionality tightly integrated with the design environment. Benefits and drawbacks of the approach will be discussed, including how designs with multiple modes of operation can be more efficiently managed.
Event details »
Digital Implementation
25 Aug 2010
Archived webinar - Are You Ready For Silicon on Insulator Design Process? Hear from ARM and Cadence
Attend this webinar to find out what SOI technology can do for you and how you can maximize its benefits. You’ll learn how to implement and verify your analog, digital, and mixed signal SOI IP and SoCs, and you’ll hear about how Cadence and its ecosystem partners are collaborating to offer an end-to-end SOI solution and methodology.
Event details »
Digital Implementation
24 Aug 2010
Archived webinar - Getting Back Timing Margins: Traditional OCV Alternatives
Attend this webinar to find alternatives to traditional OCV, what is needed to employ them, and what the tradeoffs are. Gather the information you need to make the most informed decision., what is needed to employ them, and what the tradeoffs are. You will be enables to make the more informed decision.
Event details »
Digital Implementation
29 Jul 2010
Archived webinar - Linking the Business and Electronic Component Data Domains using PTC Windchill Gateway for Cadence Allegro Design Workbench
Today’s PCB design teams commonly deploy a centralized library management group to develop and manage component information, which commonly includes schematic symbols, physical footprint, and device information (metadata). This process can quickly become a choke-point and has spawned collaborative library management solutions such as the Allegro PCB Library Workbench. However, ever-changing business data (regulatory info, purchasing info, AVL and status, device characteristics etc.), resides outside of the EDA tool environment in a corporate MRP system. Ignoring this data can lead to design errors, causing a production issue. In this webinar, you will learn how to integrate electronic and business data environments to enable a live bi-directional feed of data and a superior parts management system, resulting in fewer design spins and fewer delayed projects.
Event details »
PCB Design, IC Packaging and SiP Design
28 Jul 2010
Archived webinar - "Electronical" Co-Design between Allegro PCB Design and PTC Pro-Engineer
Many companies are incorporating sophisticated high-density electronics within more complex mechanical enclosures such as portable consumer electronics and automotive and medical devices. To design these products successfully, companies need to break down the organizational, technical, and methodology barriers that have traditionally limited design collaboration across different disciplines. Learn how to implement an ECAD/MCAD co-design methodology to enable a co-design process, bi-directional communication, and collaboration between the PCB and the enclosure design teams.
Event details »
PCB Design, IC Packaging and SiP Design
28 Jul 2010
Archived webinar - Apples vs. Apples HVL Comparison Finally Arrives: Choosing the Right Verification Language
Over the past few years, the discussion of hardware verification languages (HVLs) has come full circle. At first, verification teams tried to assess the strengths and weaknesses of individual language features ...
Event details »
System Design and Verification, Functional Verification, Enterprise Verification
29 Jun 2010
Archived webinar - Finish Your High-Performance Digital Design on Time!
Attend this webinar and find out how to finish your high-performance digital design on time. Prototype your designs effectively and use the most optimized abstraction models to implement your design with the best quality of results (QoR). Learn how a multi-CPU infrastructure allows you to achieve your turnaround time goals, what the different multi-CPU schemes are, and the advantages and disadvantages of each. Most importantly, find out how to finish your design on time by integrating the signoff engine within implementation and signoff your designs with confidence.
Event details »
Digital Implementation
23 Jun 2010
Archived webinar - Integrated 3D Full-Wave Analysis of Mixed-Signal 3D Packages
As more content is included in smaller and less expensive packages, “rules of thumb” and less sophisticated 2D extraction technology do not meet today’s design challenges. Attendees will see the value of an integrated constraint-driven design and analysis environment that includes CST’s full wave 3D extraction and characterization technology. See how changes can be easily made to the design and reanalyzed without having to leave the design environment.
Event details »
PCB Design, IC Packaging and SiP Design
16 Jun 2010
Archived webinar - Designing Mixed-Signal PCBs using Agilent ADS and the Allegro PCB RF Option
Integrating RF circuits on a mixed-signal PCB is becoming increasingly challenging, especially with shrinking design cycle times and end-product sizes. This webinar will show an easy way to integrate your RF circuits designed in Agilent ADS with the Allegro PCB Design flow. A live demonstration will show how the integration of the two tools are interoperable, and can reduce the overall design cycle time for mixed-signal PCBs with RF circuits.
Event details »
PCB Design, IC Packaging and SiP Design
09 Jun 2010
Archived webinar - Addressing DDR3 Timing Challenges
See the value of an integrated constraint-driven design and analysis environment where changes can easily be made to the design and reanalyzed without having to translate design data. This webinar will review the signal integrity (SI) design flow, focusing on the timing analysis phase. A DDR3 design will be analyzed within Allegro PCB SI, and integration with EMA TimingDesigner will allow us to detect, correct, and update the timing violation within the Allegro PCB SI environment.
Event details »
PCB Design, IC Packaging and SiP Design
24 May 2010
Archived webinar - Using RF Simulation Technologies for Analog Applications
Attend this webinar if you design power management circuits, power supplies, switched capacitor circuits, or any other analog circuits that process analog data in the presence of a fast clock. Learn how Periodic Steady State and Envelope analyses—long-proven simulation technologies for RF applications—can help speed up simulations without the slightest compromise in accuracy.
Event details »
Custom IC Design, RF Design
20 May 2010
Archived webinar - Plan Your Design to Save Time and Reduce Layer Counts
Increasing use of standards-based interfaces (DDRx, XAUI, PCI Express) are making it harder to finish routing the design in a predictable manner. Decreasing pin pitches along with an increasing number of large pin-count devices are forcing PCB designers to add layers that in many cases are unnecessary. This webinar will show users how planning your design using Allegro Interconnect Flow Planning technology can shorten design time and reduce the number of layers.
Event details »
PCB Design, IC Packaging and SiP Design
18 May 2010
Archived webinar - Analog Design in the 21st Century for Advanced Node Designs: Are you Ready?
In this webinar, we will introduce you to constraint-driven design. Constraints will maintain the “design intent” through all phases of your custom design flow: design verification, custom placement and routing, interactive editing, and layout migration. Constraints also lessen the chance of miscommunication, preventing design re-spins. Increase productivity and enable robust IP design, which preserves, enforces, and verifies the design intent. Learn about using constraints in your library and its advantages to building industry-hardened PDKs.
Event details »
Custom IC Design, RF Design
17 May 2010
Archived webinar - Enabling Technology for Custom Design: Pick the Right Process Design Kit (PDK)!
If you are a custom designer or a developer of PDKs you must attend this webinar. As process nodes advance, the design rules become more complex, the parasitic effects become acute, and the design task becomes more challenging. Today’s advanced node PDKs need to allow designers to predict parasitic effects prior to layout. Learn about the features that can be put into your PDKs to make the design process more predictable and efficient. There are several options available to choose from. In this webinar you will learn about the optimal solutions for enabling custom design with increased productivity.
Event details »
Custom IC Design
14 May 2010
Archived webinar - TLM-Driven Design and Verification Solution and Methodology
Cadence offers a comprehensive TLM-driven design and verification solution, along with adoption services, that customers are implementing successfully. Moving silicon design to higher level of abstraction to address the productivity gap by producing high-quality silicon faster, enabling greater IP reuse, and reducing functional verification costs
Event details »
System Design and Verification, Functional Verification