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 Logic Design Webinar Series
 
Type:
 Webinar
Date:
 Multiple Dates  
Location:
 Multiple Locations  


Archived Webinars
Archived webinar - Best Practices and Considerations for Accelerating Implementation of Pre-Mask and Post-Mask ECOs
01 Oct 2009 - Online       [ Register ]
This webinar will describe considerations and tradeoffs at each stage of the implementation flow, from RTL to GDSII and post-mask, for increased ECO predictability and success.
Event details »

 
Archived webinar - Prevent Chip Failures and Timing Closure Disasters! Verify and Manage your Timing Constraints for First-Pass Silicon Success!
30 Sep 2009 - Online       [ Register ]
This webinar will describe real problems experienced in today’s designs and describe a flow that provides automatic means of avoiding chip failure.
Event details »

 
Archived webinar - Prevent Chip Failures for a Low-Power Design in a Mixed-Power–Intent Design Environment
28 Sep 2009 - Online       [ Register ]
This webinar will describe real problems experienced in today's designs and how to involve alternative power formats in your proven power verification flow. It will also describe a flow that provides automatic means of avoiding chip failure.
Event details »

 
Archived webinar - How Logic Designers Can Avoid Congestion Nightmares
24 Sep 2009       [ Register ]
This webinar will outline some new automated techniques built into synthesis that identify, fix, and even prevent congestion issues, helping you take back control of your project’s success.
Event details »

 
Archived webinar - Taking the Heat off Test
23 Sep 2009 - Online       [ Register ]
This webinar will focus on a power-aware ATPG flow for nanometer IC designs from RTL to ATPG to signoff analysis. The presentation will include the critical nature of managing power during test to not only reduce high switching activity but to also avoid under-stressing the design. Specific tool capabilities and methods necessary for implementing effective solutions that also work well with test data compression will be described.
Event details »

 
Archived webinar - Linking Synthesis to ATPG: Testability as a Fourth Design Quality Parameter
21 Sep 2009 - Online       [ Register ]
Learn how Cadence solutions can help significantly improve productivity while producing a higher quality netlist for ATPG and physical implementation flows. This webinar outlines how native integration of test structure verification, test coverage analysis, and test coverage optimization functions into the Encounter® RTL Compiler logic synthesis environment achieves higher netlist quality through fewer synthesis iterations.
Event details »

 
Archived webinar - Start Your Project in the Right Direction with Pre-RTL Power Exploration
17 Sep 2009 - Online       [ Register ]
This webinar will describe how Cadence Chip Planning Solutions provide an automated environment to perform this exploration for both technical and economic tradeoffs and then to set the direction for design and implementation.
Event details »