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 Silicon Realization Webinar Series

 
Type:
Webinar
Date:
Multiple Dates  
Location:
Multiple Locations  


Archived Webinars
Archived webinar - Metric-Driven Synthesis: Collecting and Leveraging Inter and Intra Synthesis-Run Statistics to Improve Quality of Results
10 Dec 2010 11:00 AM       [ Register ]
This webinar details the specific classes of synthesis metrics that are most valuable to collect, and provides hands-on demo examples of how and why intelligently analyzing them can improve your synthesis productivity.
Event details »

 
Archived webinar - Are You Ready for Your Next-Generation Analog/Mixed-Signal Product?
09 Dec 2010 11:00 AM       [ Register ]
Attend this webinar to learn how Triune Systems takes advantage of the Cadence mixed-signal tool suite for their nanoSmart ultra–low-power green technology development (National Science Foundation funded , NSF-SBIR Grant No. 1013282). In this webinar, we will talk about the Cadence mixed-signal design and verification solution, which enables the abstraction of analog and mixed-signal designs for both architectural exploration and verification. Triune Systems will talk about this technology and some of the techniques they employ with these tools to establish design confidence for meeting aggressive time-to-market goals.
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Archived webinar - Migrating from VMM to the UVM
08 Dec 2010       [ Register ]
With the UVM 1.0 release around the corner, this is the time to plan a migration from OVM, VMM, and custom methodologies. The Accellera Verification IP Technical Subcommittee standardized an OVM-VMM interoperability Best Practices guide in July of 2009. Cadence has updated the library associated with the standard to be compatible with the UVM, and donated that back to Accellera. In addition, Cadence has upgraded the OVM-UVM migration script based on real-world customer experience. Attendees will learn about the migration planning requirements by walking through case studies of VMM and OVM migrations as well as Vera RVM to OVM/UVM. These examples will cover both the verification environment and the associated register packages.
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Archived webinar - OpenPDK: What is the Goal of this Effort, and What is the Status?
07 Dec 2010       [ Register ]
The industry is calling for a "single source" for EDA enablement. Some solutions want to enforce a particular implementation of a PDK. But this forces the entire EDA industry to comply to the same format and, in most cases, retool to comply. The OpenPDK effort is very different. OpenPDK's goal is an implementation-free, single source for EDA enablement. OpenPDK members are seeking a means to define all of the necessary process information—design rules and device definitions—into a format that can be published once and used by all EDA vendors equally. Hear Cadence and Mentor discuss their views on the OpenPDK effort.
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Archived webinar - Where Does Power Intent Come From? Create and Debug Power Intent for Low-Power Designs
06 Dec 2010       [ Register ]
This webinar will describe real problems experienced in today’s chip designs and how to create and debug power intent in your proven power verification flow.
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Archived webinar - When IP Collides, Brace for Impact on Timing Constraints and CDC! Verify and Manage Your Timing Constraints and CDCs!
03 Dec 2010       [ Register ]
This webinar will describe real problems experienced in today’s chip designs and describe a flow that provides an automatic means of avoiding chip failure.
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Archived webinar - IC 6.1: A Leap Forward in Productivity
02 Dec 2010       [ Register ]
Join us in this webinar to learn how the Cadence custom IC team took an innovative metrics-driven approach to delivering customer-proven productivity improvements in the Virtuoso 6.1 release. You will learn how to pinpoint inefficiencies in your flows, as well as some of the latest back-to-basics tips on boosting productivity.
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Archived webinar - Silicon Diagnostics – Enabling Greater Accuracy for Fast Silicon Evaluation
02 Dec 2010       [ Register ]
Process variations are greatly complicating efforts to accurately locate design-process defects for timely and profitable production. This webinar will provide an overview of how advanced diagnostics capabilities enable a more productive, intuitive silicon diagnostics process.
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Archived webinar - Managing Parasitics in the Back End
01 Dec 2010       [ Register ]
this webinar, we will go through a methodology referred to as “Rapid Analog Prototyping” that shows how to efficiently and accurately generate physical information such as parasitics without having to wait for hand-crafted layout.
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Archived webinar - Achieve the Next Level of Verification Productivity with the Specman Advanced Option
01 Dec 2010       [ Register ]
In this webinar learn about the new Specman Advanced Option that can improve your overall verification effort by 40–60%. Find out how to save hundreds of hours of simulation time using the dynamic load/re-seed capability, how to debug your e code with the performance of compiled code, and how to greatly increase productivity and system-level scalability by using the multi-core compilation capability.
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Archived webinar - A Practical Guide to Exploiting Optimization in Custom Design Flows
30 Nov 2010       [ Register ]
This webinar will briefly explore the evolution of optimization in analog design and then quickly move on to how it is used in Virtuoso technology to provide real, practical benefits to analog designers. Attendees will learn about the expanded capabilities Cadence offers and how easy it is to incorporate optimization into the design flow. Also, practical guidance will be given on where optimization works well and how to use it as a design aid.
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Archived webinar - How To Completely Eliminate SoC Connectivity Bugs (Really!)
30 Nov 2010       [ Register ]
Bugs from incorrect connectivity – whether they’re misconnected IP blocks inside an SoC or erroneous muxing of pad rings – can kill a chip as just easily as more sophisticated functional bugs. With internal connection points surpassing hundreds of thousands of nodes, the traditional approach of assigning detail-oriented summer interns to spot-check connectivity with some dynamic simulations is rapidly losing effectiveness. In this webinar, we’ll show you how to apply formal verification technology to exhaustively prove with 100% mathematical certainty that all of your SoC’s internal and external pad ring connections are completely correct.
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Archived webinar - Managing Parasitics in the Front End
19 Nov 2010       [ Register ]
This webinar features the Virtuoso Analog Design Environment GXL. Within the tool, there are facilities for you to add parasitic quantities to nets in the design, explore the effects on your measurements (including corners and statistics if you wish), and then give the implementation engineer direction on the critical nets within the design that need to be handled with care.
Event details »

 
Archived webinar - Design Techniques That Make ECOs Predictable
18 Nov 2010       [ Register ]
This webinar will discuss how automated ECO synthesis works, discuss techniques for debugging ECO synthesis problems (large patch size, failure to close timing after ECO synthesis, failure to find a valid patch), and finally discuss implementation flows that make the automated ECO synthesis process predictable.
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Archived webinar - Analog Verification—How Do You Know Your Circuit is Right? Smart Verification!
17 Nov 2010       [ Register ]
The complexity of analog and RF ICs and SoCs, combined with increasing cost pressures, means it is critical for engineers to efficiently verify complex sets of performance and operating conditions. In this webinar, we will discuss the latest methodologies and techniques available from Cadence today to improve both verification productivity and design team collaboration.
Event details »

 
Archived webinar - Are You Losing Sleep Over How to Perform Top-Level Mixed-Signal SoC Verification?
16 Nov 2010       [ Register ]
This webinar will introduce you to the Cadence mixed-signal verification environment that enables full-chip verification very close to digital speeds using real number models. You’ll also learn about mixed-signal behavioral modeling using Real/Wreal functionality in Verilog-AMS and SystemVerilog to achieve 500x performance boost for top-level SoC verification.
Event details »

 
Archived webinar - New Techniques for Debugging NonEQs and Aborts in Equivalence Checking
15 Nov 2010       [ Register ]
This webinar will provide basic background knowledge on what equivalence checking is, how it works, and what causes false non-equivalence and aborts. We will then cover new techniques for debugging non-equivalence issues and preventing aborts in equivalence checking through coding style changes, implementation flows, and verification tool setup tips.
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Archived webinar - Maximizing Your Investment in the UVM
11 Nov 2010       [ Register ]
This webinar will demonstrate the technical aspects of the UVM Reference Flow so that users can immediately employ this new environment to improve their verification productivity. Emphasis will be on making sure users understand the design and verification components, how the book explains the theory and practical aspects behind the methodology and the reference flow examples, how to run the flow, and the legal responsibilities of users who decide to incorporate the UVM Reference Flow as part of their process.
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Archived webinar - Remote Enablement for a Globalized Workforce - Cadence and Open Text Enable Optimized Performance
11 Nov 2010       [ Register ]
Attend this technical webinar to find out how Cadence and OpenText are providing a complete solution and competitive edge for companies in four key areas: Accelerate design schedules and reduce time to market; Do more work in less time; Maximize resources while reducing cost; Manage outsourced design projects. This webinar will also cover the needs to enable OpenText’s Exceed onDemand and the Cadence Virtuoso software to work together for optimal performance to help customers achieve their high level objectives of virtualization, remote access, and collaboration.
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Archived webinar - Parasitic-Aware Design: A Complete Analog Design Flow
10 Nov 2010       [ Register ]
This webinar will give you a high-level overview of the main steps involved in rapidly developing your designs and being able to deal with parasitics effectively. Each of the steps in the design, implementation, and verification of the circuits will be shown, and you will see a brief demonstration. This webinar will get you started with the proper background information to get the most out of the subsequent webinars. You will be introduced to the tools and methodology Cadence offers for parasitic-aware design analysis.
Event details »

 
Archived webinar - Metric-Driven Verification: The Galaxy Beyond Just Simulation
09 Nov 2010       [ Register ]
Let us introduce you to the galaxy of MDV solutions beyond just RTL simulation. This webinar will show you how the proven MDV approach can help you successfully verify your entire SoC design, beyond the RTL-only scope from the past.
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Archived webinar - Why Cadence Has the Best UVM Solution
02 Nov 2010       [ Register ]
In this webinar, you’ll learn how to build a multi-language UVM environment including high-performance verification engines tuned for the UVM and advanced debug and analysis. Your productivity depends heavily on the solution you choose, and Cadence has the most experience with the UVM in the industry.
Event details »

 
Archived webinar - DRC+ Now: Early DFM Signoff in the Digital Implementation Process
21 Oct 2010       [ Register ]
This joint technical webinar with GLOBALFOUNDRIES will describe what, when, why, and how designers can incorporate DRC+ into an existing digital implementation flow to achieve DFM signoff at 28nm and below. With Cadence pattern matching and automated fixing built into Encounter tools, designers can quickly identify and fix DRC+ errors, thereby avoiding potential manufacturability issues down the road. By capturing these issues early in the design flow, DRC+ provides Encounter place-and-route engineers peace of mind that their SoC design is DFM-clean.
Event details »