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 Functional Verification Webinar Series 2013

 
Type:
Webinar
Date:
Multiple Dates  
Location:
Multiple Locations  


Archived Webinars
Archived Webinar: Best Practices in Verification Planning
04 Sep 2013       [ Register ]
This webinar articulates a methodology for verification planning based on actual experience at Freescale Semiconductor. The verification planning process described in this session is streamlined for derivatives and comprehensive enough for new design and verification development. It explains a complete verification flow including verification strategy, planning, change management, and closure.
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Archived Webinar: Configurable Specman Messaging for Improved Productivity
17 Jul 2013       [ Register ]
In this webinar we will expose previous shortcomings and reflect how the new infrastructure solves those issues.
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Archived Webinar: Simplify UVM Debug with Cadence Incisive SimVision
26 Jun 2013       [ Register ]
This webinar walks you through the advantages of using the debug power of the Cadence Incisive SimVision unified graphical debugging environment within a complex, class-based SystemVerilog environment for both interactive and post-process debug. We will showcase some of the new SimVision enhancements that improve overall debug productivity.
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Archived Webinar: Introducing Low-Power Verification RAK (Rapid Adoption Kit)
19 Jun 2013       [ Register ]
This webinar walks you through the power format file using the example design provided in the RAK, and outlines the implicit logic inferred from the power intent file. You’ll also see a demo of the latest Cadence low-power verification debug applied to the example, and learn how to download the RAK for your own use.
Event details »

 
2012 Functional Verification Webinar Series
23 Feb 2012  - 11 Dec 2012      [ Details ]
Cadence verification experts are presenting a series of technical webinars on the most relevant topics in functional verification. In these concise, 1-hour sessions, our technical experts will address hot topics including the Universal Verification Methodology (UVM), low power, metric-driven verification (MDV), formal techniques, and mixed-signal verification approaches.


 
2011 Functional Verification Webinar Series
10 Mar 2011  - 11 Dec 2011      [ Details ]
Cadence verification experts are presenting a series of technical webinars on the most relevant topics in functional verification. In these concise, 1-hour sessions, our technical experts will address hot topics including the Universal Verification Methodology (UVM), low power, metric-driven verification (MDV), formal techniques, and mixed-signal verification approaches.