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 Digital Webinar Series 2012

 
Type:
Webinar
Date:
Multiple Dates  
Location:
Multiple Locations  


Archived Webinars
Archived Webinar: RTL-to-GDSII Low-Power Methodology
10 Apr 2012       [ Register ]
Attend this technical webinar and find out the latest Cadence Logic Design and Encounter Digital Implementation (EDI) System has to offer in enabling low-power designs. Learn how our intent-driven low-power methodology can significantly reduce power consumption while optimizing design team productivity and design cycle time. Meet power specifications no matter which technique you use: power shutoff, multiple supply voltages, dynamic voltage and frequency scaling, and others. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »

 
Archived Webinar: What is New in Encounter v11.1: Signoff Analysis
05 Apr 2012       [ Register ]
Attend this technical webinar and find out the latest Cadence Encounter Digital Implementation (EDI) System has to offer in enabling signoff and in-design signoff. Learn how the traditional timing, signal integrity, and power analysis signoff solutions have been enhanced to manage huge designs implemented on the most advanced process technologies. Maintain signoff accuracy for design methodologies that use double patterning; handle SoC designs with a growing number of operational modes more efficiently; and, enable efficient design flows that automate optimizations from floorplanning through pre-tapeout signoff. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »

 
Archived Webinar: What is New in Encounter v11.1: Giga-Scale Design
29 Mar 2012       [ Register ]
Attend this technical webinar and find out the latest Cadence Encounter Digital Implementation (EDI) System has to offer in enabling giga-scale designs. Learn how our GigaFlex technology can handle growing capacity requirements by extending FlexModels, FlexILMs, and FlexViews. FlexModels enable netlist compression while retaining the relevant physical and logical information, allowing for faster turnaround time and one-pass implementation handoff. FlexILMs and FlexViews enable concurrent top-and block-level optimization and final hierarchical closure, resulting in fewer iterations and a faster path to hierarchical convergence. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »

 
Archived Webinar: What is New in Encounter v11.1: 20nm Design
27 Mar 2012       [ Register ]
Attend this technical webinar and find out the latest Cadence Encounter Digital Implementation (EDI) System has to offer in enabling 20nm designs. Learn about our new 20nm double-patterning digital implementation and signoff methodology. Get ready for the next step in process manufacturing evolution and create faster, smaller, more integrated devices. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »

 
Archived webinar - What is New in Encounter v11.1: High-Performance GHz+ Design
22 Mar 2012 9:00 AM       [ Register ]
Attend this technical webinar and find out the latest Cadence Logic Design and Encounter Digital Implementation (EDI) System has to offer in enabling high-performance GHz and low-power microprocessor-based SoCs. Meet your power, performance, and area targets with physical synthesis and physical implementation technologies such as our GigaOpt optimization engine and clock concurrent optimization (CCOpt). CCOpt users are realizing up to 10% boosts in timing closure and up to 30% improvements in power and area. Enhance your productivity, time to market, and competitive advantage. Attend this webinar and find out how to enable your next SoC with Cadence technologies.
Event details »