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Cadence Annual "ClubT"

06 Oct 2008  
Cadence AB, Isafjordsgatan 30C, SE-164 40 Kista, Sweden  

Duration: 1 day - 9am to 4pm
Agenda includes lunch and a concluding networking happy hour.

Space is limited—Register today!

It is the time of the year again where we would like to give you an update on verification solutions with Specman, Incisive Enterprise Simulator, VIP, and future "Trailblazer" technology roadmap in our annual "ClubT" event series.

This free event runs from 9am to 4pm, and includes lunch and a concluding networking happy hour.

Who should attend
  • Verification engineers
  • Verification engineering management
  • Logic designers with verification experience
You will learn how to

Join us for this free, one-day event to learn more about:
  • Metric Driven Verification
    • See how the time tested Coverage Driven Verification ("CDV") process is being be expanded into to consider critical verification metrics beyond functional and RTL code coverage
    • Learn how the new "Enterprise Planner" can automate and simplify metrics-based verification planning; as well as keep you on top of any sudden changes to the DUT or test plan specification
    • Examples will include integration of metrics from formal and dynamic ABV, firmware verification, and analog/mixed-signal coverage points can all be recorded in a new SQL database
  • How the Open Verification Methodology (OVM) expands to support multiple languages – e, SystemVerilog, and SystemC
    • OVM enhancements including the new OVM e open source library
    • AOP vs. OOP coding style within an OVM framework
    • Reusing and interconnecting e and SystemVerilog verification components in multi-language testbenches
    • Cadence extended multi-language OVM VIP Portfolio – more "out-of-the-box" metric driven verification with the Compliance Management System (CMS)
  • The latest Incisive enhancements for testbench developments with e and SystemVerilog
    • Updates on the tools and processes you use every day
    • Customer reports on how users are applying new capabilities introduced in past ClubT’s, such as the "IntelliGen" generator, Incisive Software Extensions ("ISX") for HW/SW co-verification, AMS designs, and Low Power Verification
  • Trailblazer Futures: Innovations needed to verify 1 billion logic gate SoCs
    In the near future, you can design & implement anything you can think of (i.e. surprisingly, process nodes/manufacturing will not be a bottleneck) But will you be able to verify your 1 billion gate monster?

    In short, verification will continue to be the bottleneck in the product development process. In this section we will introduce some new technologies and methodologies Cadence is working on to prepare you for verifying 1 billion logic gate SoCs, as well as show what you can do today to set yourself up for future success.

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