Home > About Cadence > Events > Event Details

Cadence Technology on Tour: Club SV

 
Type:
Technology on Tour  
Date:
15 Sep 2014  
Location:
Herzliya, Israel  

We are proud to invite you to our Club SystemVerilog (ClubSV) event featuring solutions to some of the most important challenges in SoC verification. Cadence R&D, application engineers, and product management representatives will share new methodologies and technologies mixing presentations, demos, and interactive discussions. Among the topics that will be covered are maximizing simulation performance, applying advanced debug techniques, and managing complex, multi-site verification projects. After you attend you will have new information you can apply immediately from the Incisive 14.1 release and will have insight into what’s coming in 14.2.

If you are a verification and/or design engineer working with SystemVerilog, this is THE event for you. If you are a verification manager, IP/SoC director, or project manager, it is a great opportunity to come, bring your verification team and sharpen their skills and knowledge.

This is a great opportunity for you to meet and network with verification users, share experiences, ideas, insights, and gather information on the best available verification solutions from Cadence.

Agenda
08:30 – 09:00 Registration
09:00 – 09:30 Welcome and Cadence verification roadmap
09:30 – 10:45 Maximizing performance including SystemVerilog and UVM
10:45 – 11:30 Maximizing performance using SystemVerilog constraints
11:30 – 11:45 Break
11:45 – 13:00 Applying advanced debug including UVM and Incisive Debug Analyzer
13:00 – 13:45 Lunch
13:45 – 14:30 Verifying complex protocols with Cadence Verification IP (VIP)
14:30 – 15:00 Managing complex, multi-site verification with the new vManager
15:00 – 15:15 Break
15:15 – 15:45 Reset verification using x-propagation
15:45 – 16:15 UVM 1.2 update
16:15 – 16:30 Club SV summary

Questions About this Event?
Send email to marketing_euro@cadence.com