Home > About Cadence > Events > Event Details

DesignCon China 2014

 
Type:
Industry Conference  
Date:
01 Sep 2014  
Location:
Shenzhen  

DesignCon is the largest educational conference and technology exhibition for chip, board, and systems design engineers in the high-speed communications and semiconductor communities. IIC China introduced its DesignCon China Conference last year, providing attendees intensive technical learning and networking opportunities.

Visit Cadence in booth #4A14 to see demonstrations of our Allegro® Sigrity™ solutions for signal integrity and power integrity. Find out how the integration of Voltus™ and Sigrity tools provides a complete solution to power delivery, from chip to the entire system.

Also, don’t miss the Cadence® speaker sessions:

Topic: Extending Chip Power Integrity Analysis into a System Signoff Solution
Cadence Speaker: Yun Dai
Date: Thursday, September 4th
Time: 09:50am – 10:30am
Overview:

Validating the required power integrity on the entire PDN system requires co-aimulation and co-analysis technologies from both chip and system analysis tools. In this presentation, we will highlight how Cadence’s Voltus and Sigrity technologies work together to analyze the power grid for the entire chip-package-PCB PDN system. We will discuss the co-simulation flow and include in our presentation real design examples that involve traditional EMIR and more advanced electrical-thermal analysis for 3D-IC technologies. Our Voltus (chip) and Sigrity (system) tools provide the signoff analysis technology and Cadence Virtuoso®, Encounter®, and Allegro implementation tools can be used to correct any problems found.

Topic: DDR4 Challenges: Allegro and Sigrity Front-to-Back System Signoff Solution
Cadence Speaker: Fang Li
Date: Thursday, September 4th
Time: 1:30pm – 2:10pm
Overview:

This presentation covers how Cadence’s Allegro and Sigrity technologies can be used throughout the design process to address the challenges of designing with DDR4 memory. Attend the session to learn more about interface objects with embedded constraints used in design authoring that drive implementation, as well as implementation technology that understands the challenges of DDR4 PCB routing. You’ll also gain deeper insights into Sigrity technology, which is aligned with the latest JEDEC electrical requirements for DDR4, including bit error rate (BER) requirements. See how Allegro and Sigrity technologies support an efficient and effective DDR4 front-to-back system signoff solution for designs requiring high-performance memory interfaces.

Questions About this Event?
Send email to event_cn@cadence.com