will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.
Home > About Cadence > Events > Event Details

Technology on Tour Singapore 2014

Cadence Event  
15 Aug 2014 8:00 AM  
Marina Mandarin Singapore Hotel, Singapore  

Join Cadence at Singapore’s Marina Mandarin Singapore hotel for the annual Technology on Tour event. The latest technologies and methodologies will be covered in three tracks on custom IC and mixed signal, digital, and silicon/package/board (SPB).

Custom IC and Mixed-Signal Track
This track introduces the latest custom IC and mixed-signal technologies. In addition to the introduction of new technologies for productivity and flow enhancements such Electrically Aware Designs (EAD) and Symbolic Placement of Devices (SPD), the latest methodologies in mixed-signal simulations and library characterization will also be presented.

Digital Track
In this track, we will provide the latest updates for our Incisive® Enterprise Simulator and also present ways to maximize verification efficiency using Metric-Driven Verification (MDV). There will also be an introduction on our latest timing and power analysis tools, Tempus™ Timing Signoff Solution and Voltus™ IC Power Integrity Solution. The Tempus solution provides full-chip silicon-accurate timing signoff and signal integrity analysis, while the Voltus solution is a high-capacity, accurate, and fast tool for debugging full-chip power-consumption, IR drop, and electromigration issues.

SPB Track
In this track, the latest PCB and Sigrity™ features and roadmap will be presented. It will also include new features and methodologies in the design of IC packaging using Allegro® Package Designer. Presentations on Sigrity technology include signal/power integrity analysis and extraction of transmission lines using the Sigrity PowerSI® 3D electromagnetic field solver.



General Session
Common session for all 3 tracks: update on Cadence technology roadmap and introduction to analog, digital, and memory IPs

Registration & Welcome Breakfast
Cadence® Update
Cadence Application-Optimized IP Solutions Overview

Cadence Memory Interface IP Solutions

Morning Tea Break


Custom IC and Mixed-Signal Track

Digital Track

SPB Track

Mixed-Signal Update: Mixed-Signal Characterization with Virtuoso® Liberate™ Maximizing Verification Efficiency Using Metric-Driven Verification (including Incisive vManager™ Solution)
Allegro and Sigrity Roadmap
Mixed-Signal Update: Mixed-Signal Characterization with Virtuoso® Liberate™ (Cont) Verification Performance 2014 Roadmap
What’s New: Allegro PCB and IC Packaging
Analog/Mixed-Signal and Lower Power Simulation
Cadence Incisive Enterprise Simulator (IES) Update Multi-Fabric Planning with SIP, OrbitIO™, and Allegro Solutions
Custom IC Update: Layout Productivity with Cadence Virtuoso Technology, Including: EAD, LDE, SPD Advanced Process Node Signoff with Tempus™ Timing Signoff Solution
SI/PI Design Checking and Verification
Afternoon Tea Break
Custom IC Update (Cont)
  • IC 6.1 Update
  • In-Design Physical Verification Signoff
  • RAKs
Tackling Your Power Signoff Challenges with Voltus™ Platform – Performance, Capacity, and Design Closure 3DEM Extraction for Long Transmission Line
Wrap-up and Lucky Draw
Lucky Draw Official Rules

Questions About this Event?
Send email to