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Tapping Into High-Level Synthesis for Improved Time to Market, Quality of Results, and IP Reuse Recorded Webinar

Original webinar date:
08 Jul 2014 9:00 AM  
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Design and verification engineers worldwide have used the Cadence high-level synthesis (HLS) solutions to produce silicon in products found in your home, office, and pocket. Learn how HLS is being used to achieve 10X more productivity, 5X faster verification speed and better effectiveness, and 20% better Quality of Results in terms of area, performance, and power. You'll also learn how HLS helps to deliver the promise of IP reuse by designing at a higher level of abstraction.

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